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https://github.com/torvalds/linux.git
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Several fixes for:
- external irq on non-DT boards - cpuidle code in some circumstances - PMC code in relation with PLLB/PLL_UTMI/USB: mainly for SAMA5D3 and AT91SAM9N12 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAABAgAGBQJRyuyOAAoJEAf03oE53VmQDOgIALT6Ql8reZiaLcB9cuhpPVy1 vJAx8jxmJy0V1eXiD/Gl00261vb2tw7YJK9gt3zfLP0upqsYWrV5sV7f8UhR73RQ rrJSfWfLkPFPBORYyKiHw9kWQUMBczybz9hhv3HbbxdVHmpD7LnaPRWXat71u1u/ Uh8UpF5d2s3lAE1BBqTr9Ec6n3r7vKqI/0MO2pWnyf11nfNZMI705zG9ehrQZHZx v8hovwjWuQ/o06GD45xMJuunEp6IVHl01A2ZRcppuvQD4CtNBXo3AnlNLQ6TK7iz 9qOVhAiD8/1Td3CXSOOMiInCDBIVOXI/bbkKrAFJcTgGdL1jkAKEN3A1xUxXYVQ= =28Xo -----END PGP SIGNATURE----- Merge tag 'at91-fixes' of git://github.com/at91linux/linux-at91 into next/fixes-non-critical From Nicolas Ferre: Several fixes for: - external irq on non-DT boards - cpuidle code in some circumstances - PMC code in relation with PLLB/PLL_UTMI/USB: mainly for SAMA5D3 and AT91SAM9N12 * tag 'at91-fixes' of git://github.com/at91linux/linux-at91: ARM: at91/PMC: use at91_usb_rate() for UTMI PLL ARM: at91/PMC: fix at91sam9n12 USB FS init ARM: at91/PMC: at91sam9n12 family has a PLLB ARM: at91/PMC: sama5d3 family doesn't have a PLLB ARM: at91: cpuidle: Fix target_residency ARM: at91: fix at91_extern_irq usage for non-dt boards Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
6b9a39de73
@ -332,10 +332,6 @@ static void __init at91rm9200_initialize(void)
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{
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arm_pm_idle = at91rm9200_idle;
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arm_pm_restart = at91rm9200_restart;
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at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
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| (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
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| (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
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| (1 << AT91RM9200_ID_IRQ6);
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/* Initialize GPIO subsystem */
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at91_gpio_init(at91rm9200_gpio,
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@ -388,6 +384,10 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
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AT91_SOC_START(at91rm9200)
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.map_io = at91rm9200_map_io,
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.default_irq_priority = at91rm9200_default_irq_priority,
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.extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
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| (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
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| (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
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| (1 << AT91RM9200_ID_IRQ6),
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.ioremap_registers = at91rm9200_ioremap_registers,
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.register_clocks = at91rm9200_register_clocks,
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.init = at91rm9200_initialize,
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@ -348,8 +348,6 @@ static void __init at91sam9260_initialize(void)
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{
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arm_pm_idle = at91sam9_idle;
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arm_pm_restart = at91sam9_alt_restart;
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at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
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| (1 << AT91SAM9260_ID_IRQ2);
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/* Register GPIO subsystem */
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at91_gpio_init(at91sam9260_gpio, 3);
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@ -400,6 +398,8 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
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AT91_SOC_START(at91sam9260)
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.map_io = at91sam9260_map_io,
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.default_irq_priority = at91sam9260_default_irq_priority,
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.extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
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| (1 << AT91SAM9260_ID_IRQ2),
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.ioremap_registers = at91sam9260_ioremap_registers,
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.register_clocks = at91sam9260_register_clocks,
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.init = at91sam9260_initialize,
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@ -290,8 +290,6 @@ static void __init at91sam9261_initialize(void)
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{
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arm_pm_idle = at91sam9_idle;
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arm_pm_restart = at91sam9_alt_restart;
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at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
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| (1 << AT91SAM9261_ID_IRQ2);
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/* Register GPIO subsystem */
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at91_gpio_init(at91sam9261_gpio, 3);
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@ -342,6 +340,8 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
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AT91_SOC_START(at91sam9261)
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.map_io = at91sam9261_map_io,
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.default_irq_priority = at91sam9261_default_irq_priority,
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.extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
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| (1 << AT91SAM9261_ID_IRQ2),
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.ioremap_registers = at91sam9261_ioremap_registers,
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.register_clocks = at91sam9261_register_clocks,
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.init = at91sam9261_initialize,
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@ -327,7 +327,6 @@ static void __init at91sam9263_initialize(void)
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{
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arm_pm_idle = at91sam9_idle;
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arm_pm_restart = at91sam9_alt_restart;
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at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
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/* Register GPIO subsystem */
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at91_gpio_init(at91sam9263_gpio, 5);
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@ -378,6 +377,7 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
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AT91_SOC_START(at91sam9263)
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.map_io = at91sam9263_map_io,
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.default_irq_priority = at91sam9263_default_irq_priority,
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.extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1),
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.ioremap_registers = at91sam9263_ioremap_registers,
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.register_clocks = at91sam9263_register_clocks,
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.init = at91sam9263_initialize,
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@ -374,7 +374,6 @@ static void __init at91sam9g45_initialize(void)
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{
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arm_pm_idle = at91sam9_idle;
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arm_pm_restart = at91sam9g45_restart;
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at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
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/* Register GPIO subsystem */
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at91_gpio_init(at91sam9g45_gpio, 5);
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@ -425,6 +424,7 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
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AT91_SOC_START(at91sam9g45)
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.map_io = at91sam9g45_map_io,
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.default_irq_priority = at91sam9g45_default_irq_priority,
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.extern_irq = (1 << AT91SAM9G45_ID_IRQ0),
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.ioremap_registers = at91sam9g45_ioremap_registers,
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.register_clocks = at91sam9g45_register_clocks,
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.init = at91sam9g45_initialize,
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@ -293,7 +293,6 @@ static void __init at91sam9rl_initialize(void)
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{
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arm_pm_idle = at91sam9_idle;
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arm_pm_restart = at91sam9_alt_restart;
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at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
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/* Register GPIO subsystem */
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at91_gpio_init(at91sam9rl_gpio, 4);
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@ -344,6 +343,7 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
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AT91_SOC_START(at91sam9rl)
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.map_io = at91sam9rl_map_io,
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.default_irq_priority = at91sam9rl_default_irq_priority,
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.extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
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.ioremap_registers = at91sam9rl_ioremap_registers,
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.register_clocks = at91sam9rl_register_clocks,
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.init = at91sam9rl_initialize,
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@ -55,8 +55,6 @@ static void at91x40_idle(void)
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void __init at91x40_initialize(unsigned long main_clock)
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{
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arm_pm_idle = at91x40_idle;
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at91_extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
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| (1 << AT91X40_ID_IRQ2);
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}
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/*
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@ -86,9 +84,10 @@ static unsigned int at91x40_default_irq_priority[NR_AIC_IRQS] __initdata = {
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void __init at91x40_init_interrupts(unsigned int priority[NR_AIC_IRQS])
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{
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u32 extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
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| (1 << AT91X40_ID_IRQ2);
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if (!priority)
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priority = at91x40_default_irq_priority;
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at91_aic_init(priority, at91_extern_irq);
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at91_aic_init(priority, extern_irq);
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}
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@ -75,7 +75,7 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
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#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
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|| cpu_is_at91sam9g45() \
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|| cpu_is_at91sam9x5() \
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|| cpu_is_at91sam9n12()))
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|| cpu_is_sama5d3()))
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#define cpu_has_upll() (cpu_is_at91sam9g45() \
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|| cpu_is_at91sam9x5() \
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@ -489,7 +489,7 @@ static int at91_clk_show(struct seq_file *s, void *unused)
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seq_printf(s, "UCKR = %8x\n", uckr);
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}
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seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
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if (cpu_has_upll())
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if (cpu_has_upll() || cpu_is_at91sam9n12())
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seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB));
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seq_printf(s, "SR = %8x\n", sr);
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@ -614,6 +614,8 @@ static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
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{
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if (pll == &pllb && (reg & AT91_PMC_USB96M))
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return freq / 2;
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else if (pll == &utmi_clk || cpu_is_at91sam9n12())
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return freq / (1 + ((reg & AT91_PMC_OHCIUSBDIV) >> 8));
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else
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return freq;
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}
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@ -683,6 +685,8 @@ static struct clk *const standard_pmc_clocks[] __initconst = {
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/* PLLB generated USB full speed clock init */
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static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
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{
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unsigned int reg;
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/*
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* USB clock init: choose 48 MHz PLLB value,
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* disable 48MHz clock during usb peripheral suspend.
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@ -691,22 +695,35 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
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*/
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uhpck.parent = &pllb;
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at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
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reg = at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2);
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pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
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if (cpu_is_at91rm9200()) {
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reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
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uhpck.pmc_mask = AT91RM9200_PMC_UHP;
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udpck.pmc_mask = AT91RM9200_PMC_UDP;
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at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
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} else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
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cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
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cpu_is_at91sam9g10()) {
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reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
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uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
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udpck.pmc_mask = AT91SAM926x_PMC_UDP;
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} else if (cpu_is_at91sam9n12()) {
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/* Divider for USB clock is in USB clock register for 9n12 */
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reg = AT91_PMC_USBS_PLLB;
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/* For PLLB output 96M, set usb divider 2 (USBDIV + 1) */
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reg |= AT91_PMC_OHCIUSBDIV_2;
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at91_pmc_write(AT91_PMC_USB, reg);
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/* Still setup masks */
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uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
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udpck.pmc_mask = AT91SAM926x_PMC_UDP;
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}
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at91_pmc_write(AT91_CKGR_PLLBR, 0);
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udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
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uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
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udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
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uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
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}
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/* UPLL generated USB full speed clock init */
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@ -725,8 +742,7 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
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/* Now set uhpck values */
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uhpck.parent = &utmi_clk;
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uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
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uhpck.rate_hz = utmi_clk.rate_hz;
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uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
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uhpck.rate_hz = at91_usb_rate(&utmi_clk, utmi_clk.rate_hz, usbr);
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}
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static int __init at91_pmc_init(unsigned long main_clock)
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@ -51,7 +51,7 @@ static struct cpuidle_driver at91_idle_driver = {
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.states[1] = {
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.enter = at91_enter_idle,
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.exit_latency = 10,
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.target_residency = 100000,
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.target_residency = 10000,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "RAM_SR",
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.desc = "WFI and DDR Self Refresh",
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@ -85,4 +85,4 @@ extern void __init at91_gpio_irq_setup(void);
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extern int __init at91_gpio_of_irq_setup(struct device_node *node,
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struct device_node *parent);
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extern int at91_extern_irq;
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extern u32 at91_get_extern_irq(void);
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@ -130,7 +130,10 @@ extern void __iomem *at91_pmc_base;
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#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
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#define AT91_PMC_USBS_PLLA (0 << 0)
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#define AT91_PMC_USBS_UPLL (1 << 0)
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#define AT91_PMC_USBS_PLLB (1 << 0) /* [AT91SAMN12 only] */
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#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
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#define AT91_PMC_OHCIUSBDIV_1 (0x0 << 8)
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#define AT91_PMC_OHCIUSBDIV_2 (0x1 << 8)
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#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */
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#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */
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@ -232,7 +232,14 @@ static void __maybe_unused at91_aic5_eoi(struct irq_data *d)
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at91_aic_write(AT91_AIC5_EOICR, 0);
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}
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unsigned long *at91_extern_irq;
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static unsigned long *at91_extern_irq;
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u32 at91_get_extern_irq(void)
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{
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if (!at91_extern_irq)
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return 0;
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return *at91_extern_irq;
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}
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#define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq)
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@ -212,7 +212,7 @@ static int at91_pm_enter(suspend_state_t state)
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(at91_pmc_read(AT91_PMC_PCSR)
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| (1 << AT91_ID_FIQ)
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| (1 << AT91_ID_SYS)
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| (at91_extern_irq))
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| (at91_get_extern_irq()))
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& at91_aic_read(AT91_AIC_IMR),
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state);
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@ -48,7 +48,7 @@ void __init at91_init_irq_default(void)
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void __init at91_init_interrupts(unsigned int *priority)
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{
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/* Initialize the AIC interrupt controller */
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at91_aic_init(priority, at91_extern_irq);
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at91_aic_init(priority, at91_boot_soc.extern_irq);
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/* Enable GPIO interrupts */
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at91_gpio_irq_setup();
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@ -6,6 +6,7 @@
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struct at91_init_soc {
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int builtin;
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u32 extern_irq;
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unsigned int *default_irq_priority;
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void (*map_io)(void);
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void (*ioremap_registers)(void);
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