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ARM: sun5i: a13: Add display and TCON clocks
Enable the display and TCON (channel 0 and channel 1) clocks that are going to be needed to drive the display engine, tcon and TV encoders. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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6b70991043
@ -61,8 +61,8 @@
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0";
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clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
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<&dram_gates 26>;
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clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&de_be_clk>,
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<&tcon_ch0_clk>, <&dram_gates 26>;
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status = "disabled";
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};
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};
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@ -170,6 +170,41 @@
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"dram_ace",
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"dram_iep";
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};
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de_be_clk: clk@01c20104 {
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#clock-cells = <0>;
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#reset-cells = <0>;
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compatible = "allwinner,sun4i-a10-display-clk";
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reg = <0x01c20104 0x4>;
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clocks = <&pll3>, <&pll7>, <&pll5 1>;
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clock-output-names = "de-be";
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};
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de_fe_clk: clk@01c2010c {
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#clock-cells = <0>;
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#reset-cells = <0>;
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compatible = "allwinner,sun4i-a10-display-clk";
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reg = <0x01c2010c 0x4>;
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clocks = <&pll3>, <&pll7>, <&pll5 1>;
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clock-output-names = "de-fe";
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};
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tcon_ch0_clk: clk@01c20118 {
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#clock-cells = <0>;
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#reset-cells = <1>;
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compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
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reg = <0x01c20118 0x4>;
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clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
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clock-output-names = "tcon-ch0-sclk";
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};
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tcon_ch1_clk: clk@01c2012c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
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reg = <0x01c2012c 0x4>;
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clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
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clock-output-names = "tcon-ch1-sclk";
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};
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};
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soc@01c00000 {
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@ -51,8 +51,9 @@
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0-tve0";
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clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
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<&ahb_gates 44>, <&dram_gates 26>;
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clocks = <&ahb_gates 34>, <&ahb_gates 36>,
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<&ahb_gates 44>, <&de_be_clk>,
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<&tcon_ch1_clk>, <&dram_gates 26>;
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status = "disabled";
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};
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};
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