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PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus
TI keystone is the only Designware driver using .scan_bus(). This function pointer is the only thing preventing the Designware driver from using pci_host_probe(). Let's use the pci_ops.add_bus hook instead. Link: https://lore.kernel.org/r/20200821035420.380495-16-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com>
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@ -454,15 +454,19 @@ static struct pci_ops ks_child_pcie_ops = {
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};
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};
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/**
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/**
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* ks_pcie_v3_65_scan_bus() - keystone scan_bus post initialization
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* ks_pcie_v3_65_add_bus() - keystone add_bus post initialization
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*
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*
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* This sets BAR0 to enable inbound access for MSI_IRQ register
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* This sets BAR0 to enable inbound access for MSI_IRQ register
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*/
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*/
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static void ks_pcie_v3_65_scan_bus(struct pcie_port *pp)
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static int ks_pcie_v3_65_add_bus(struct pci_bus *bus)
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{
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{
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struct pcie_port *pp = bus->sysdata;
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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if (!pci_is_root_bus(bus))
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return 0;
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/* Configure and set up BAR0 */
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/* Configure and set up BAR0 */
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ks_pcie_set_dbi_mode(ks_pcie);
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ks_pcie_set_dbi_mode(ks_pcie);
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@ -477,12 +481,15 @@ static void ks_pcie_v3_65_scan_bus(struct pcie_port *pp)
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* be sufficient. Use physical address to avoid any conflicts.
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* be sufficient. Use physical address to avoid any conflicts.
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*/
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*/
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
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return 0;
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}
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}
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static struct pci_ops ks_pcie_ops = {
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static struct pci_ops ks_pcie_ops = {
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.map_bus = dw_pcie_own_conf_map_bus,
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.map_bus = dw_pcie_own_conf_map_bus,
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.read = pci_generic_config_read,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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.write = pci_generic_config_write,
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.add_bus = ks_pcie_v3_65_add_bus,
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};
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};
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/**
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/**
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@ -842,7 +849,6 @@ static int __init ks_pcie_host_init(struct pcie_port *pp)
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static const struct dw_pcie_host_ops ks_pcie_host_ops = {
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static const struct dw_pcie_host_ops ks_pcie_host_ops = {
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.host_init = ks_pcie_host_init,
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.host_init = ks_pcie_host_init,
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.msi_host_init = ks_pcie_msi_host_init,
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.msi_host_init = ks_pcie_msi_host_init,
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.scan_bus = ks_pcie_v3_65_scan_bus,
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};
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};
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static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = {
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static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = {
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