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Blackfin arch: fix bug cplbmgr.S does not exit properly on error condition
https://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=1685 Ensure that cache/protection is turned back on when we get a fault, and ensure that the initial population of the CPLB tables are correct - that kernel is locked in CPLB tables Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
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@ -163,8 +163,8 @@ static struct cplb_desc cplb_data[] = {
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static u16 __init lock_kernel_check(u32 start, u32 end)
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{
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if ((start <= (u32) _stext && end >= (u32) _end)
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|| (start >= (u32) _stext && end <= (u32) _end))
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if ((end <= (u32) _end && end >= (u32)_stext) ||
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(start <= (u32) _end && start >= (u32)_stext))
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return IN_KERNEL;
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return 0;
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}
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@ -670,8 +670,8 @@ void dump_bfin_regs(struct pt_regs *fp, void *retaddr)
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printk("\n");
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} else
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printk("\n" KERN_NOTICE
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"Cannot look at the [PC] for it is"
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" in unreadable memory - sorry\n");
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"Cannot look at the [PC] <%p> for it is"
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" in unreadable memory - sorry\n", retaddr);
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printk(KERN_NOTICE "\n" KERN_NOTICE "SEQUENCER STATUS:\n");
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printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n",
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@ -73,7 +73,7 @@ ENTRY(_cplb_mgr)
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/* ICPLB Miss Exception. We need to choose one of the
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* currently-installed CPLBs, and replace it with one
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* from the configuration table.
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*/
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*/
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P4.L = LO(ICPLB_FAULT_ADDR);
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P4.H = HI(ICPLB_FAULT_ADDR);
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@ -222,7 +222,7 @@ ENTRY(_cplb_mgr)
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/* See if failed address > start address */
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CC = R4 <= R0(IU);
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IF !CC JUMP .Linext;
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IF !CC JUMP .Linext;
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/* extract page size (17:16)*/
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R3 = EXTRACT(R2, R1.L) (Z);
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@ -271,16 +271,27 @@ ENTRY(_cplb_mgr)
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/* FAILED CASES*/
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.Lno_page_in_table:
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( R7:4,P5:3 ) = [SP++];
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R0 = CPLB_NO_ADDR_MATCH;
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RTS;
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JUMP .Lfail_ret;
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.Lall_locked:
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( R7:4,P5:3 ) = [SP++];
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R0 = CPLB_NO_UNLOCKED;
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RTS;
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JUMP .Lfail_ret;
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.Lprot_violation:
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( R7:4,P5:3 ) = [SP++];
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R0 = CPLB_PROT_VIOL;
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.Lfail_ret:
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/* Make sure we turn protection/cache back on, even in the failing case */
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BITSET(R5,ENICPLB_P);
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CLI R2;
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SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
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.align 8;
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[P4] = R5;
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SSYNC;
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STI R2;
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( R7:4,P5:3 ) = [SP++];
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RTS;
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.Ldcplb_write:
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