From f220d3ebba8343dcbd8c83e4bb4fa6fbcfc616c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 21 Jan 2018 17:12:31 +0100 Subject: [PATCH 01/13] arm64: dts: actions: Convert to new-style SPDX license identifiers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move SPDX-License-Identifier to the top and add one for the Makefile. Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/actions/Makefile | 2 ++ arch/arm64/boot/dts/actions/s900-bubblegum-96.dts | 3 +-- arch/arm64/boot/dts/actions/s900.dtsi | 3 +-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/actions/Makefile b/arch/arm64/boot/dts/actions/Makefile index d8b923480f5a..b57fd2372ecd 100644 --- a/arch/arm64/boot/dts/actions/Makefile +++ b/arch/arm64/boot/dts/actions/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ + dtb-$(CONFIG_ARCH_ACTIONS) += s700-cubieboard7.dtb dtb-$(CONFIG_ARCH_ACTIONS) += s900-bubblegum-96.dtb diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts index 21ca80f9941c..562d89df811c 100644 --- a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts +++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts @@ -1,7 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2017 Andreas Färber - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /dts-v1/; diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi index 11406f6d3a6d..0b287c51f9ba 100644 --- a/arch/arm64/boot/dts/actions/s900.dtsi +++ b/arch/arm64/boot/dts/actions/s900.dtsi @@ -1,7 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2017 Andreas Färber - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ #include From d1ca7c56e1617ffeff71e9ba521254b8ffdeda59 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 11 Apr 2018 22:10:33 +0530 Subject: [PATCH 02/13] dt-bindings: power: Add Actions Semi S900 SPS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define power domains for Actions Semi S900 SoC Smart Power System (SPS). Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Signed-off-by: Andreas Färber --- .../bindings/power/actions,owl-sps.txt | 2 ++ .../dt-bindings/power/owl-s900-powergate.h | 23 +++++++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 include/dt-bindings/power/owl-s900-powergate.h diff --git a/Documentation/devicetree/bindings/power/actions,owl-sps.txt b/Documentation/devicetree/bindings/power/actions,owl-sps.txt index 78edd63641e8..a3571937b019 100644 --- a/Documentation/devicetree/bindings/power/actions,owl-sps.txt +++ b/Documentation/devicetree/bindings/power/actions,owl-sps.txt @@ -3,11 +3,13 @@ Actions Semi Owl Smart Power System (SPS) Required properties: - compatible : "actions,s500-sps" for S500 "actions,s700-sps" for S700 + "actions,s900-sps" for S900 - reg : Offset and length of the register set for the device. - #power-domain-cells : Must be 1. See macros in: include/dt-bindings/power/owl-s500-powergate.h for S500 include/dt-bindings/power/owl-s700-powergate.h for S700 + include/dt-bindings/power/owl-s900-powergate.h for S900 Example: diff --git a/include/dt-bindings/power/owl-s900-powergate.h b/include/dt-bindings/power/owl-s900-powergate.h new file mode 100644 index 000000000000..d939bd964657 --- /dev/null +++ b/include/dt-bindings/power/owl-s900-powergate.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */ +/* + * Actions Semi S900 SPS + * + * Copyright (c) 2018 Linaro Ltd. + */ +#ifndef DT_BINDINGS_POWER_OWL_S900_POWERGATE_H +#define DT_BINDINGS_POWER_OWL_S900_POWERGATE_H + +#define S900_PD_GPU_B 0 +#define S900_PD_VCE 1 +#define S900_PD_SENSOR 2 +#define S900_PD_VDE 3 +#define S900_PD_HDE 4 +#define S900_PD_USB3 5 +#define S900_PD_DDR0 6 +#define S900_PD_DDR1 7 +#define S900_PD_DE 8 +#define S900_PD_NAND 9 +#define S900_PD_USB2_H0 10 +#define S900_PD_USB2_H1 11 + +#endif From 4db4a57fe01bfb50e7fe3b810a297527f0942548 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 7 Nov 2017 01:15:51 +0530 Subject: [PATCH 03/13] arm64: dts: actions: s900: Add Clock Management Unit nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Actions Semi S900 Clock Management Unit (CMU) nodes. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/actions/s900.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi index 0b287c51f9ba..19ccad4faae8 100644 --- a/arch/arm64/boot/dts/actions/s900.dtsi +++ b/arch/arm64/boot/dts/actions/s900.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2017 Andreas Färber */ +#include #include / { @@ -87,6 +88,18 @@ #clock-cells = <0>; }; + losc: losc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + diff24M: diff24M { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -153,6 +166,13 @@ status = "disabled"; }; + cmu: clock-controller@e0160000 { + compatible = "actions,s900-cmu"; + reg = <0x0 0xe0160000 0x0 0x1000>; + clocks = <&hosc>, <&losc>; + #clock-cells = <1>; + }; + timer: timer@e0228000 { compatible = "actions,s900-timer"; reg = <0x0 0xe0228000 0x0 0x8000>; From d3105e47b5192d7986b1af03874402aa2b2acd00 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 9 Feb 2018 22:54:37 +0530 Subject: [PATCH 04/13] arm64: dts: actions: s900: Source CMU clock for UARTs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove fixed clock in Bubblegum-96 board and source CMU (Clock Management Unit) clock for UART nodes in Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam [AF: Move/add clocks to SoC] Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/actions/s900-bubblegum-96.dts | 7 ------- arch/arm64/boot/dts/actions/s900.dtsi | 7 +++++++ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts index 562d89df811c..84d42dc07787 100644 --- a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts +++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts @@ -23,12 +23,6 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; - - uart5_clk: uart5-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &timer { @@ -37,5 +31,4 @@ &uart5 { status = "okay"; - clocks = <&uart5_clk>; }; diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi index 19ccad4faae8..f254b1843db2 100644 --- a/arch/arm64/boot/dts/actions/s900.dtsi +++ b/arch/arm64/boot/dts/actions/s900.dtsi @@ -120,6 +120,7 @@ uart0: serial@e0120000 { compatible = "actions,s900-uart", "actions,owl-uart"; reg = <0x0 0xe0120000 0x0 0x2000>; + clocks = <&cmu CLK_UART0>; interrupts = ; status = "disabled"; }; @@ -127,6 +128,7 @@ uart1: serial@e0122000 { compatible = "actions,s900-uart", "actions,owl-uart"; reg = <0x0 0xe0122000 0x0 0x2000>; + clocks = <&cmu CLK_UART1>; interrupts = ; status = "disabled"; }; @@ -134,6 +136,7 @@ uart2: serial@e0124000 { compatible = "actions,s900-uart", "actions,owl-uart"; reg = <0x0 0xe0124000 0x0 0x2000>; + clocks = <&cmu CLK_UART2>; interrupts = ; status = "disabled"; }; @@ -141,6 +144,7 @@ uart3: serial@e0126000 { compatible = "actions,s900-uart", "actions,owl-uart"; reg = <0x0 0xe0126000 0x0 0x2000>; + clocks = <&cmu CLK_UART3>; interrupts = ; status = "disabled"; }; @@ -148,6 +152,7 @@ uart4: serial@e0128000 { compatible = "actions,s900-uart", "actions,owl-uart"; reg = <0x0 0xe0128000 0x0 0x2000>; + clocks = <&cmu CLK_UART4>; interrupts = ; status = "disabled"; }; @@ -155,6 +160,7 @@ uart5: serial@e012a000 { compatible = "actions,s900-uart", "actions,owl-uart"; reg = <0x0 0xe012a000 0x0 0x2000>; + clocks = <&cmu CLK_UART5>; interrupts = ; status = "disabled"; }; @@ -162,6 +168,7 @@ uart6: serial@e012c000 { compatible = "actions,s900-uart", "actions,owl-uart"; reg = <0x0 0xe012c000 0x0 0x2000>; + clocks = <&cmu CLK_UART6>; interrupts = ; status = "disabled"; }; From 6bd9ad12a3c91a972dbc877fbc8a212f02dec7ba Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 11 Apr 2018 22:10:34 +0530 Subject: [PATCH 05/13] arm64: dts: actions: s900: Add SPS node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Actions Semi S900 Smart Power System (SPS) node. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/actions/s900.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi index f254b1843db2..e09a95d576cb 100644 --- a/arch/arm64/boot/dts/actions/s900.dtsi +++ b/arch/arm64/boot/dts/actions/s900.dtsi @@ -173,6 +173,12 @@ status = "disabled"; }; + sps: power-controller@e012e000 { + compatible = "actions,s900-sps"; + reg = <0x0 0xe012e000 0x0 0x2000>; + #power-domain-cells = <1>; + }; + cmu: clock-controller@e0160000 { compatible = "actions,s900-cmu"; reg = <0x0 0xe0160000 0x0 0x1000>; From a1d8219f97f3093e9abe31a7cb55b721e11956b1 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 4 Apr 2018 22:52:50 +0530 Subject: [PATCH 06/13] arm64: dts: actions: s900: Add pinctrl node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add pinctrl nodes for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Linus Walleij Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/actions/s900.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi index e09a95d576cb..962ade5777e8 100644 --- a/arch/arm64/boot/dts/actions/s900.dtsi +++ b/arch/arm64/boot/dts/actions/s900.dtsi @@ -186,6 +186,12 @@ #clock-cells = <1>; }; + pinctrl: pinctrl@e01b0000 { + compatible = "actions,s900-pinctrl"; + reg = <0x0 0xe01b0000 0x0 0x1000>; + clocks = <&cmu CLK_GPIO>; + }; + timer: timer@e0228000 { compatible = "actions,s900-timer"; reg = <0x0 0xe0228000 0x0 0x8000>; From 48d4c88471ab4db37433345506827ce44e21cb59 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sun, 20 May 2018 10:47:33 +0530 Subject: [PATCH 07/13] arm64: dts: actions: s900: Add gpio properties to pinctrl node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add gpio properties to pinctrl node for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Linus Walleij Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/actions/s900.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi index 962ade5777e8..83be1ad3fd2a 100644 --- a/arch/arm64/boot/dts/actions/s900.dtsi +++ b/arch/arm64/boot/dts/actions/s900.dtsi @@ -190,6 +190,9 @@ compatible = "actions,s900-pinctrl"; reg = <0x0 0xe01b0000 0x0 0x1000>; clocks = <&cmu CLK_GPIO>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 146>; + #gpio-cells = <2>; }; timer: timer@e0228000 { From 29ea7bae209ebdd17873c15a381db951672d696e Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sun, 20 May 2018 10:47:34 +0530 Subject: [PATCH 08/13] arm64: dts: actions: s900-bubblegum-96: Add gpio line names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add gpio line names to Actions Semi S900 based Bubblegum-96 board. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Linus Walleij Signed-off-by: Andreas Färber --- .../boot/dts/actions/s900-bubblegum-96.dts | 175 ++++++++++++++++++ 1 file changed, 175 insertions(+) diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts index 84d42dc07787..ca17182edd8f 100644 --- a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts +++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts @@ -25,6 +25,181 @@ }; }; +/* + * GPIO name legend: proper name = the GPIO line is used as GPIO + * NC = not connected (pin out but not routed from the chip to + * anything the board) + * "[PER]" = pin is muxed for [peripheral] (not GPIO) + * LSEC = Low Speed External Connector + * HSEC = High Speed External Connector + * + * Line names are taken from the schematic "Schematics Bubblegum96" + * version v1.0 + * + * For the lines routed to the external connectors the + * lines are named after the 96Boards CE Specification 1.0, + * Appendix "Expansion Connector Signal Description". + * + * When the 96Boards naming of a line and the schematic name of + * the same line are in conflict, the 96Boards specification + * takes precedence, which means that the external UART on the + * LSEC is named UART0 while the schematic and SoC names this + * UART2. Only exception is the I2C lines for which the schematic + * naming has been preferred. This is only for the informational + * lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L" + * are the only ones actually used for GPIO. + */ + +&pinctrl { + gpio-line-names = + "GPIO-A", /* GPIO_0, LSEC pin 23 */ + "GPIO-B", /* GPIO_1, LSEC pin 24 */ + "GPIO-C", /* GPIO_2, LSEC pin 25 */ + "GPIO-D", /* GPIO_3, LSEC pin 26 */ + "GPIO-E", /* GPIO_4, LSEC pin 27 */ + "GPIO-F", /* GPIO_5, LSEC pin 28 */ + "GPIO-G", /* GPIO_6, LSEC pin 29 */ + "GPIO-H", /* GPIO_7, LSEC pin 30 */ + "GPIO-I", /* GPIO_8, LSEC pin 31 */ + "GPIO-J", /* GPIO_9, LSEC pin 32 */ + "NC", /* GPIO_10 */ + "NC", /* GPIO_11 */ + "SIRQ2_1V8", /* GPIO_12 */ + "PCM0_OUT", /* GPIO_13 */ + "WIFI_LED", /* GPIO_14 */ + "PCM0_SYNC", /* GPIO_15 */ + "PCM0_CLK", /* GPIO_16 */ + "PCM0_IN", /* GPIO_17 */ + "BT_LED", /* GPIO_18 */ + "LED0", /* GPIO_19 */ + "LED1", /* GPIO_20 */ + "JTAG_TCK", /* GPIO_21 */ + "JTAG_TMS", /* GPIO_22 */ + "JTAG_TDI", /* GPIO_23 */ + "JTAG_TDO", /* GPIO_24 */ + "[UART1_RxD]", /* GPIO_25, LSEC pin 13 */ + "NC", /* GPIO_26 */ + "[UART1_TxD]", /* GPIO_27, LSEC pin 11 */ + "SD0_D0", /* GPIO_28 */ + "SD0_D1", /* GPIO_29 */ + "SD0_D2", /* GPIO_30 */ + "SD0_D3", /* GPIO_31 */ + "SD1_D0", /* GPIO_32 */ + "SD1_D1", /* GPIO_33 */ + "SD1_D2", /* GPIO_34 */ + "SD1_D3", /* GPIO_35 */ + "SD0_CMD", /* GPIO_36 */ + "SD0_CLK", /* GPIO_37 */ + "SD1_CMD", /* GPIO_38 */ + "SD1_CLK", /* GPIO_39 */ + "SPI0_SCLK", /* GPIO_40, LSEC pin 8 */ + "SPI0_CS", /* GPIO_41, LSEC pin 12 */ + "SPI0_DIN", /* GPIO_42, LSEC pin 10 */ + "SPI0_DOUT", /* GPIO_43, LSEC pin 14 */ + "I2C5_SDATA", /* GPIO_44, HSEC pin 36 */ + "I2C5_SCLK", /* GPIO_45, HSEC pin 38 */ + "UART0_RX", /* GPIO_46, LSEC pin 7 */ + "UART0_TX", /* GPIO_47, LSEC pin 5 */ + "UART0_RTSB", /* GPIO_48, LSEC pin 9 */ + "UART0_CTSB", /* GPIO_49, LSEC pin 3 */ + "I2C4_SCLK", /* GPIO_50, HSEC pin 32 */ + "I2C4_SDATA", /* GPIO_51, HSEC pin 34 */ + "I2C0_SCLK", /* GPIO_52 */ + "I2C0_SDATA", /* GPIO_53 */ + "I2C1_SCLK", /* GPIO_54, LSEC pin 15 */ + "I2C1_SDATA", /* GPIO_55, LSEC pin 17 */ + "I2C2_SCLK", /* GPIO_56, LSEC pin 19 */ + "I2C2_SDATA", /* GPIO_57, LSEC pin 21 */ + "CSI0_DN0", /* GPIO_58, HSEC pin 10 */ + "CSI0_DP0", /* GPIO_59, HSEC pin 8 */ + "CSI0_DN1", /* GPIO_60, HSEC pin 16 */ + "CSI0_DP1", /* GPIO_61, HSEC pin 14 */ + "CSI0_CN", /* GPIO_62, HSEC pin 4 */ + "CSI0_CP", /* GPIO_63, HSEC pin 2 */ + "CSI0_DN2", /* GPIO_64, HSEC pin 22 */ + "CSI0_DP2", /* GPIO_65, HSEC pin 20 */ + "CSI0_DN3", /* GPIO_66, HSEC pin 28 */ + "CSI0_DP3", /* GPIO_67, HSEC pin 26 */ + "[CLK0]", /* GPIO_68, HSEC pin 15 */ + "CSI1_DN0", /* GPIO_69, HSEC pin 44 */ + "CSI1_DP0", /* GPIO_70, HSEC pin 42 */ + "CSI1_DN1", /* GPIO_71, HSEC pin 50 */ + "CSI1_DP1", /* GPIO_72, HSEC pin 48 */ + "CSI1_CN", /* GPIO_73, HSEC pin 56 */ + "CSI1_CP", /* GPIO_74, HSEC pin 54 */ + "[CLK1]", /* GPIO_75, HSEC pin 17 */ + "[GPIOD0]", /* GPIO_76 */ + "[GPIOD1]", /* GPIO_77 */ + "BT_RST_N", /* GPIO_78 */ + "EXT_DC_EN", /* GPIO_79 */ + "[PCM_DI]", /* GPIO_80, LSEC pin 22 */ + "[PCM_DO]", /* GPIO_81, LSEC pin 20 */ + "[PCM_CLK]", /* GPIO_82, LSEC pin 18 */ + "[PCM_FS]", /* GPIO_83, LSEC pin 16 */ + "WAKE_BT", /* GPIO_84 */ + "WL_REG_ON", /* GPIO_85 */ + "NC", /* GPIO_86 */ + "NC", /* GPIO_87 */ + "NC", /* GPIO_88 */ + "NC", /* GPIO_89 */ + "NC", /* GPIO_90 */ + "WIFI_WAKE", /* GPIO_91 */ + "BT_WAKE", /* GPIO_92 */ + "NC", /* GPIO_93 */ + "OTG_EN2", /* GPIO_94 */ + "OTG_EN", /* GPIO_95 */ + "DSI_DP3", /* GPIO_96, HSEC pin 45 */ + "DSI_DN3", /* GPIO_97, HSEC pin 47 */ + "DSI_DP1", /* GPIO_98, HSEC pin 33 */ + "DSI_DN1", /* GPIO_99, HSEC pin 35 */ + "DSI_CP", /* GPIO_100, HSEC pin 21 */ + "DSI_CN", /* GPIO_101, HSEC pin 23 */ + "DSI_DP0", /* GPIO_102, HSEC pin 27 */ + "DSI_DN0", /* GPIO_103, HSEC pin 29 */ + "DSI_DP2", /* GPIO_104, HSEC pin 39 */ + "DSI_DN2", /* GPIO_105, HSEC pin 41 */ + "N0_D0", /* GPIO_106 */ + "N0_D1", /* GPIO_107 */ + "N0_D2", /* GPIO_108 */ + "N0_D3", /* GPIO_109 */ + "N0_D4", /* GPIO_110 */ + "N0_D5", /* GPIO_111 */ + "N0_D6", /* GPIO_112 */ + "N0_D7", /* GPIO_113 */ + "N0_DQS", /* GPIO_114 */ + "N0_DQSN", /* GPIO_115 */ + "NC", /* GPIO_116 */ + "NC", /* GPIO_117 */ + "NC", /* GPIO_118 */ + "N0_CEB1", /* GPIO_119 */ + "CARD_DT", /* GPIO_120 */ + "N0_CEB3", /* GPIO_121 */ + "SD_DAT0", /* GPIO_122, HSEC pin 1 */ + "SD_DAT1", /* GPIO_123, HSEC pin 3 */ + "SD_DAT2", /* GPIO_124, HSEC pin 5 */ + "SD_DAT3", /* GPIO_125, HSEC pin 7 */ + "NC", /* GPIO_126 */ + "NC", /* GPIO_127 */ + "[PWR_BTN_N]", /* GPIO_128, LSEC pin 4 */ + "[RST_BTN_N]", /* GPIO_129, LSEC pin 6 */ + "NC", /* GPIO_130 */ + "SD_CMD", /* GPIO_131 */ + "GPIO-L", /* GPIO_132, LSEC pin 34 */ + "GPIO-K", /* GPIO_133, LSEC pin 33 */ + "NC", /* GPIO_134 */ + "SD_SCLK", /* GPIO_135 */ + "NC", /* GPIO_136 */ + "JTAG_TRST", /* GPIO_137 */ + "I2C3_SCLK", /* GPIO_138 */ + "LED2", /* GPIO_139 */ + "LED3", /* GPIO_140 */ + "I2C3_SDATA", /* GPIO_141 */ + "UART3_RX", /* GPIO_142 */ + "UART3_TX", /* GPIO_143 */ + "UART3_RTSB", /* GPIO_144 */ + "UART3_CTSB"; /* GPIO_145 */ +}; + &timer { clocks = <&hosc>; }; From 5eb76e8a29cdbe44999c94617d17ecdd0ffc6263 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 1 Aug 2018 23:32:29 +0530 Subject: [PATCH 09/13] arm64: dts: actions: s900: Add I2C controller nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add I2C controller nodes for Actions Semiconductor S900 SoC. Signed-off-by: Manivannan Sadhasivam [AF: Squashed/added clocks, dropped pinctrl properties for now] Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/actions/s900.dtsi | 60 +++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi index 83be1ad3fd2a..d2f6d37f9177 100644 --- a/arch/arm64/boot/dts/actions/s900.dtsi +++ b/arch/arm64/boot/dts/actions/s900.dtsi @@ -186,6 +186,66 @@ #clock-cells = <1>; }; + i2c0: i2c@e0170000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0170000 0 0x1000>; + clocks = <&cmu CLK_I2C0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e0172000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0172000 0 0x1000>; + clocks = <&cmu CLK_I2C1>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e0174000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0174000 0 0x1000>; + clocks = <&cmu CLK_I2C2>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e0176000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0176000 0 0x1000>; + clocks = <&cmu CLK_I2C3>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e0178000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0178000 0 0x1000>; + clocks = <&cmu CLK_I2C4>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@e017a000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe017a000 0 0x1000>; + clocks = <&cmu CLK_I2C5>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pinctrl: pinctrl@e01b0000 { compatible = "actions,s900-pinctrl"; reg = <0x0 0xe01b0000 0x0 0x1000>; From 07b308eee06e9dacdfc2b54746613e838bef582d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 1 Aug 2018 23:32:28 +0530 Subject: [PATCH 10/13] arm64: dts: actions: s900-bubblegum-96: Enable I2C1 and I2C2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add pinctrl definitions for Actions Semiconductor S900 I2C controllers. Pinctrl definitions are only available for I2C0, I2C1, and I2C2. Enable I2C1 and I2C2 exposed on the low speed expansion connector in Bubblegum-96 board. Signed-off-by: Manivannan Sadhasivam [AF: Squashed] Signed-off-by: Andreas Färber --- .../boot/dts/actions/s900-bubblegum-96.dts | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts index ca17182edd8f..732daaa6e9d3 100644 --- a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts +++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts @@ -25,6 +25,24 @@ }; }; +&i2c0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_default>; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_default>; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_default>; +}; + /* * GPIO name legend: proper name = the GPIO line is used as GPIO * NC = not connected (pin out but not routed from the chip to @@ -198,6 +216,31 @@ "UART3_TX", /* GPIO_143 */ "UART3_RTSB", /* GPIO_144 */ "UART3_CTSB"; /* GPIO_145 */ + + i2c0_default: i2c0-default { + pinmux { + groups = "i2c0_mfp"; + function = "i2c0"; + }; + pinconf { + pins = "i2c0_sclk", "i2c0_sdata"; + bias-pull-up; + }; + }; + + i2c1_default: i2c1-default { + pinconf { + pins = "i2c1_sclk", "i2c1_sdata"; + bias-pull-up; + }; + }; + + i2c2_default: i2c2-default { + pinconf { + pins = "i2c2_sclk", "i2c2_sdata"; + bias-pull-up; + }; + }; }; &timer { From c432aaa2b28fbd28d837ec142c78e744956ef71c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 21 Sep 2018 12:03:59 -0700 Subject: [PATCH 11/13] arm64: dts: actions: s900: Add DMA Controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add DMA controller node for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/actions/s900.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi index d2f6d37f9177..491ddccc9038 100644 --- a/arch/arm64/boot/dts/actions/s900.dtsi +++ b/arch/arm64/boot/dts/actions/s900.dtsi @@ -261,5 +261,18 @@ interrupts = ; interrupt-names = "timer1"; }; + + dma: dma-controller@e0260000 { + compatible = "actions,s900-dma"; + reg = <0x0 0xe0260000 0x0 0x1000>; + interrupts = , + , + , + ; + #dma-cells = <1>; + dma-channels = <12>; + dma-requests = <46>; + clocks = <&cmu CLK_DMAC>; + }; }; }; From 8ba92cf5933507d1af6422d7421448fbf8c9981f Mon Sep 17 00:00:00 2001 From: Saravanan Sekar Date: Thu, 19 Jul 2018 11:06:48 +0200 Subject: [PATCH 12/13] arm64: dts: actions: s700: Add Clock Management Unit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Clock Management Unit for Actions Semi S700 SoC. Signed-off-by: Parthiban Nallathambi Signed-off-by: Saravanan Sekar Reviewed-by: Manivannan Sadhasivam Signed-off-by: Manivannan Sadhasivam Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/actions/s700.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi index 66dd5309f0a2..0b04c5582213 100644 --- a/arch/arm64/boot/dts/actions/s700.dtsi +++ b/arch/arm64/boot/dts/actions/s700.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2017 Andreas Färber */ +#include #include / { @@ -87,6 +88,12 @@ #clock-cells = <0>; }; + losc: losc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -153,6 +160,13 @@ status = "disabled"; }; + cmu: clock-controller@e0168000 { + compatible = "actions,s700-cmu"; + reg = <0x0 0xe0168000 0x0 0x1000>; + clocks = <&hosc>, <&losc>; + #clock-cells = <1>; + }; + sps: power-controller@e01b0100 { compatible = "actions,s700-sps"; reg = <0x0 0xe01b0100 0x0 0x100>; From 01463ac63b53e24e4e315aa9c5f091e9e0342ad4 Mon Sep 17 00:00:00 2001 From: Saravanan Sekar Date: Thu, 19 Jul 2018 11:06:49 +0200 Subject: [PATCH 13/13] arm64: dts: actions: s700: Set UART clock references from CMU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove fixed clock in Cubieboard 7 and use Clock Management Unit clocks for all UART nodes in Actions Semi S700 SoC. Signed-off-by: Parthiban Nallathambi Signed-off-by: Saravanan Sekar Reviewed-by: Manivannan Sadhasivam Signed-off-by: Manivannan Sadhasivam [AF: Moved/added to SoC] Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/actions/s700-cubieboard7.dts | 7 ------- arch/arm64/boot/dts/actions/s700.dtsi | 7 +++++++ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts index ef79d7905f44..28f3f4a0f7f0 100644 --- a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts +++ b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts @@ -28,12 +28,6 @@ device_type = "memory"; reg = <0x1 0xe0000000 0x0 0x0>; }; - - uart3_clk: uart3-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &timer { @@ -42,5 +36,4 @@ &uart3 { status = "okay"; - clocks = <&uart3_clk>; }; diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi index 0b04c5582213..192c7b39c8c1 100644 --- a/arch/arm64/boot/dts/actions/s700.dtsi +++ b/arch/arm64/boot/dts/actions/s700.dtsi @@ -114,6 +114,7 @@ uart0: serial@e0120000 { compatible = "actions,s900-uart", "actions,owl-uart"; reg = <0x0 0xe0120000 0x0 0x2000>; + clocks = <&cmu CLK_UART0>; interrupts = ; status = "disabled"; }; @@ -121,6 +122,7 @@ uart1: serial@e0122000 { compatible = "actions,s900-uart", "actions,owl-uart"; reg = <0x0 0xe0122000 0x0 0x2000>; + clocks = <&cmu CLK_UART1>; interrupts = ; status = "disabled"; }; @@ -128,6 +130,7 @@ uart2: serial@e0124000 { compatible = "actions,s900-uart", "actions,owl-uart"; reg = <0x0 0xe0124000 0x0 0x2000>; + clocks = <&cmu CLK_UART2>; interrupts = ; status = "disabled"; }; @@ -135,6 +138,7 @@ uart3: serial@e0126000 { compatible = "actions,s900-uart", "actions,owl-uart"; reg = <0x0 0xe0126000 0x0 0x2000>; + clocks = <&cmu CLK_UART3>; interrupts = ; status = "disabled"; }; @@ -142,6 +146,7 @@ uart4: serial@e0128000 { compatible = "actions,s900-uart", "actions,owl-uart"; reg = <0x0 0xe0128000 0x0 0x2000>; + clocks = <&cmu CLK_UART4>; interrupts = ; status = "disabled"; }; @@ -149,6 +154,7 @@ uart5: serial@e012a000 { compatible = "actions,s900-uart", "actions,owl-uart"; reg = <0x0 0xe012a000 0x0 0x2000>; + clocks = <&cmu CLK_UART5>; interrupts = ; status = "disabled"; }; @@ -156,6 +162,7 @@ uart6: serial@e012c000 { compatible = "actions,s900-uart", "actions,owl-uart"; reg = <0x0 0xe012c000 0x0 0x2000>; + clocks = <&cmu CLK_UART6>; interrupts = ; status = "disabled"; };