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iommufd 6.13 first rc pull
- Correct typos in comments - Elaborate a comment about how the uAPI works for IOMMU_HW_INFO_TYPE_ARM_SMMUV3 - Fix a double free on error path and add test coverage for the bug -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQRRRCHOFoQz/8F5bUaFwuHvBreFYQUCZ1Hx1QAKCRCFwuHvBreF YRA6AQCtirCoWoMgq1mSsFjtzmr5XCffS1g6T7KsKs54sDZZXAD/doa4NpE3LTPo huOPMfH2O0HufLpj+FTzew4q0RbAJAc= =z0Ak -----END PGP SIGNATURE----- Merge tag 'for-linus-iommufd' of git://git.kernel.org/pub/scm/linux/kernel/git/jgg/iommufd Pull iommufd fixes from Jason Gunthorpe: "One bug fix and some documentation updates: - Correct typos in comments - Elaborate a comment about how the uAPI works for IOMMU_HW_INFO_TYPE_ARM_SMMUV3 - Fix a double free on error path and add test coverage for the bug" * tag 'for-linus-iommufd' of git://git.kernel.org/pub/scm/linux/kernel/git/jgg/iommufd: iommu/arm-smmu-v3: Improve uAPI comment for IOMMU_HW_INFO_TYPE_ARM_SMMUV3 iommufd/selftest: Cover IOMMU_FAULT_QUEUE_ALLOC in iommufd_fail_nth iommufd: Fix out_fput in iommufd_fault_alloc() iommufd: Fix typos in kernel-doc comments
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6a103867b9
@ -420,8 +420,6 @@ out_put_fdno:
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put_unused_fd(fdno);
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out_fput:
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fput(filep);
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refcount_dec(&fault->obj.users);
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iommufd_ctx_put(fault->ictx);
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out_abort:
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iommufd_object_abort_and_destroy(ucmd->ictx, &fault->obj);
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@ -297,7 +297,7 @@ struct iommu_ioas_unmap {
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* ioctl(IOMMU_OPTION_HUGE_PAGES)
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* @IOMMU_OPTION_RLIMIT_MODE:
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* Change how RLIMIT_MEMLOCK accounting works. The caller must have privilege
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* to invoke this. Value 0 (default) is user based accouting, 1 uses process
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* to invoke this. Value 0 (default) is user based accounting, 1 uses process
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* based accounting. Global option, object_id must be 0
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* @IOMMU_OPTION_HUGE_PAGES:
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* Value 1 (default) allows contiguous pages to be combined when generating
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@ -390,7 +390,7 @@ struct iommu_vfio_ioas {
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* @IOMMU_HWPT_ALLOC_PASID: Requests a domain that can be used with PASID. The
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* domain can be attached to any PASID on the device.
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* Any domain attached to the non-PASID part of the
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* device must also be flaged, otherwise attaching a
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* device must also be flagged, otherwise attaching a
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* PASID will blocked.
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* If IOMMU does not support PASID it will return
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* error (-EOPNOTSUPP).
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@ -558,16 +558,25 @@ struct iommu_hw_info_vtd {
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* For the details of @idr, @iidr and @aidr, please refer to the chapters
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* from 6.3.1 to 6.3.6 in the SMMUv3 Spec.
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*
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* User space should read the underlying ARM SMMUv3 hardware information for
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* the list of supported features.
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* This reports the raw HW capability, and not all bits are meaningful to be
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* read by userspace. Only the following fields should be used:
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*
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* Note that these values reflect the raw HW capability, without any insight if
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* any required kernel driver support is present. Bits may be set indicating the
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* HW has functionality that is lacking kernel software support, such as BTM. If
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* a VMM is using this information to construct emulated copies of these
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* registers it should only forward bits that it knows it can support.
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* idr[0]: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN , CD2L, ASID16, TTF
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* idr[1]: SIDSIZE, SSIDSIZE
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* idr[3]: BBML, RIL
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* idr[5]: VAX, GRAN64K, GRAN16K, GRAN4K
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*
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* In future, presence of required kernel support will be indicated in flags.
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* - S1P should be assumed to be true if a NESTED HWPT can be created
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* - VFIO/iommufd only support platforms with COHACC, it should be assumed to be
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* true.
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* - ATS is a per-device property. If the VMM describes any devices as ATS
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* capable in ACPI/DT it should set the corresponding idr.
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*
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* This list may expand in future (eg E0PD, AIE, PBHA, D128, DS etc). It is
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* important that VMMs do not read bits outside the list to allow for
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* compatibility with future kernels. Several features in the SMMUv3
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* architecture are not currently supported by the kernel for nesting: HTTU,
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* BTM, MPAM and others.
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*/
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struct iommu_hw_info_arm_smmuv3 {
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__u32 flags;
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@ -766,7 +775,7 @@ struct iommu_hwpt_vtd_s1_invalidate {
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};
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/**
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* struct iommu_viommu_arm_smmuv3_invalidate - ARM SMMUv3 cahce invalidation
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* struct iommu_viommu_arm_smmuv3_invalidate - ARM SMMUv3 cache invalidation
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* (IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3)
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* @cmd: 128-bit cache invalidation command that runs in SMMU CMDQ.
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* Must be little-endian.
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@ -615,7 +615,12 @@ TEST_FAIL_NTH(basic_fail_nth, access_pin_domain)
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/* device.c */
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TEST_FAIL_NTH(basic_fail_nth, device)
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{
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struct iommu_hwpt_selftest data = {
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.iotlb = IOMMU_TEST_IOTLB_DEFAULT,
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};
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struct iommu_test_hw_info info;
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uint32_t fault_id, fault_fd;
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uint32_t fault_hwpt_id;
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uint32_t ioas_id;
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uint32_t ioas_id2;
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uint32_t stdev_id;
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@ -678,6 +683,15 @@ TEST_FAIL_NTH(basic_fail_nth, device)
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if (_test_cmd_vdevice_alloc(self->fd, viommu_id, idev_id, 0, &vdev_id))
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return -1;
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if (_test_ioctl_fault_alloc(self->fd, &fault_id, &fault_fd))
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return -1;
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close(fault_fd);
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if (_test_cmd_hwpt_alloc(self->fd, idev_id, hwpt_id, fault_id,
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IOMMU_HWPT_FAULT_ID_VALID, &fault_hwpt_id,
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IOMMU_HWPT_DATA_SELFTEST, &data, sizeof(data)))
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return -1;
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return 0;
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}
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