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MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DT
Rather than hardcoding the IRQ number used to cascade interrupts from the SoC interrupt controller to the CPU interrupt controller, read that IRQ number from the DT describing the system. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Brian Norris <computersforpeace@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/10137/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -85,6 +85,11 @@ static int __init jz4740_intc_of_init(struct device_node *node,
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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int parent_irq;
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parent_irq = irq_of_parse_and_map(node, 0);
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if (!parent_irq)
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return -EINVAL;
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jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
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@ -108,7 +113,7 @@ static int __init jz4740_intc_of_init(struct device_node *node,
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irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, IRQ_NOPROBE | IRQ_LEVEL);
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setup_irq(2, &jz4740_cascade_action);
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setup_irq(parent_irq, &jz4740_cascade_action);
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return 0;
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}
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IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", jz4740_intc_of_init);
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