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MIPS: Emulate the new MIPS R6 BEQZC and JIC instructions

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MIPS R6 uses the <R6 ldc2 opcode for the new BEQZC and JIC instructions

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
This commit is contained in:
Markos Chandras 2014-11-27 09:32:25 +00:00
parent 84fef63012
commit 69b9a2fd05
3 changed files with 16 additions and 1 deletions
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2
arch/mips/include/uapi/asm/inst.h
View File

@ -32,7 +32,7 @@ enum major_op {
sb_op, sh_op, swl_op, sw_op,
sdl_op, sdr_op, swr_op, cache_op,
ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
lld_op, ldc1_op, ldc2_op, ld_op,
lld_op, ldc1_op, ldc2_op, beqzcjic_op = ldc2_op, ld_op,
sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op,
scd_op, sdc1_op, sdc2_op, sd_op
};

8
arch/mips/kernel/branch.c
View File

@ -799,6 +799,14 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
epc += 4 + (insn.i_format.simmediate << 2);
regs->cp0_epc = epc;
break;
case beqzcjic_op:
if (!cpu_has_mips_r6) {
ret = -SIGILL;
break;
}
/* Compact branch: BEQZC || JIC */
regs->cp0_epc += 8;
break;
#endif
case cbcond0_op:
case cbcond1_op:

7
arch/mips/math-emu/cp1emu.c
View File

@ -678,6 +678,13 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
*contpc = regs->cp0_epc + dec_insn.pc_inc +
dec_insn.next_pc_inc;
return 1;
case beqzcjic_op:
if (!cpu_has_mips_r6)
break;
*contpc = regs->cp0_epc + dec_insn.pc_inc +
dec_insn.next_pc_inc;
return 1;
#endif
case cop0_op: