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RISC-V: improve string-function assembly
Adapt the suggestions for the assembly string functions that Andrew suggested but that I didn't manage to include into the series that got applied. This includes improvements to two comments, removal of unneeded labels and moving one instruction slightly higher to contradict an explanatory comment. Suggested-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230208225328.1636017-3-heiko@sntech.de Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -40,7 +40,9 @@ SYM_FUNC_START(strcmp)
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ret
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/*
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* Variant of strcmp using the ZBB extension if available
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* Variant of strcmp using the ZBB extension if available.
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* The code was published as part of the bitmanip manual
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* in Appendix A.
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*/
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#ifdef CONFIG_RISCV_ISA_ZBB
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strcmp_zbb:
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@ -57,7 +59,7 @@ strcmp_zbb:
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* a1 - string2
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*
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* Clobbers
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* t0, t1, t2, t3, t4, t5
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* t0, t1, t2, t3, t4
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*/
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or t2, a0, a1
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@ -96,7 +96,7 @@ strlen_zbb:
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* of valid bytes in this chunk.
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*/
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srli a0, t1, 3
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bgtu t3, a0, 3f
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bgtu t3, a0, 2f
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/* Prepare for the word comparison loop. */
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addi t2, t0, SZREG
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@ -112,20 +112,20 @@ strlen_zbb:
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addi t0, t0, SZREG
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orc.b t1, t1
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beq t1, t3, 1b
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2:
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not t1, t1
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CZ t1, t1
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srli t1, t1, 3
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/* Get number of processed words. */
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/* Get number of processed bytes. */
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sub t2, t0, t2
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/* Add number of characters in the first word. */
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add a0, a0, t2
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srli t1, t1, 3
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/* Add number of characters in the last word. */
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add a0, a0, t1
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3:
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2:
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ret
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.option pop
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@ -70,7 +70,7 @@ strncmp_zbb:
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li t5, -1
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and t2, t2, SZREG-1
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add t4, a0, a2
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bnez t2, 4f
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bnez t2, 3f
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/* Adjust limit for fast-path. */
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andi t6, t4, -SZREG
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@ -114,23 +114,21 @@ strncmp_zbb:
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ret
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/* Simple loop for misaligned strings. */
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3:
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/* Restore limit for slow-path. */
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.p2align 3
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4:
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bge a0, t4, 6f
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3:
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bge a0, t4, 5f
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lbu t0, 0(a0)
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lbu t1, 0(a1)
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addi a0, a0, 1
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addi a1, a1, 1
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bne t0, t1, 5f
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bnez t0, 4b
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bne t0, t1, 4f
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bnez t0, 3b
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5:
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4:
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sub a0, t0, t1
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ret
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6:
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5:
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li a0, 0
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ret
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