powerpc: Change CONFIG_E500 to CONFIG_PPC_E500

It will be used outside arch/powerpc, make it clear its a
powerpc configuration item.

And we already have CONFIG_PPC_E500MC, so that will make
it more consistent.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/e63b22083c11c4300f4a82d3123a46e5fdd54fa6.1663606876.git.christophe.leroy@csgroup.eu
This commit is contained in:
Christophe Leroy 2022-09-19 19:01:35 +02:00 committed by Michael Ellerman
parent 1df399012b
commit 688de017ef
18 changed files with 38 additions and 38 deletions

View File

@ -210,7 +210,7 @@ KBUILD_CFLAGS += $(call cc-option,-mno-string)
cpu-as-$(CONFIG_40x) += -Wa,-m405 cpu-as-$(CONFIG_40x) += -Wa,-m405
cpu-as-$(CONFIG_44x) += -Wa,-m440 cpu-as-$(CONFIG_44x) += -Wa,-m440
cpu-as-$(CONFIG_ALTIVEC) += $(call as-option,-Wa$(comma)-maltivec) cpu-as-$(CONFIG_ALTIVEC) += $(call as-option,-Wa$(comma)-maltivec)
cpu-as-$(CONFIG_E500) += -Wa,-me500 cpu-as-$(CONFIG_PPC_E500) += -Wa,-me500
# When using '-many -mpower4' gas will first try and find a matching power4 # When using '-many -mpower4' gas will first try and find a matching power4
# mnemonic and failing that it will allow any valid mnemonic that GAS knows # mnemonic and failing that it will allow any valid mnemonic that GAS knows

View File

@ -510,7 +510,7 @@ enum {
#elif defined(CONFIG_44x) #elif defined(CONFIG_44x)
CPU_FTRS_44X | CPU_FTRS_440x6 | CPU_FTRS_44X | CPU_FTRS_440x6 |
#endif #endif
#ifdef CONFIG_E500 #ifdef CONFIG_PPC_E500
CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500 | CPU_FTRS_E500_2 |
#endif #endif
#ifdef CONFIG_PPC_E500MC #ifdef CONFIG_PPC_E500MC
@ -584,7 +584,7 @@ enum {
#elif defined(CONFIG_44x) #elif defined(CONFIG_44x)
CPU_FTRS_44X & CPU_FTRS_440x6 & CPU_FTRS_44X & CPU_FTRS_440x6 &
#endif #endif
#ifdef CONFIG_E500 #ifdef CONFIG_PPC_E500
CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500 & CPU_FTRS_E500_2 &
#endif #endif
#ifdef CONFIG_PPC_E500MC #ifdef CONFIG_PPC_E500MC

View File

@ -52,7 +52,7 @@ static inline void arch_kgdb_breakpoint(void)
/* On non-E500 family PPC32 we determine the size by picking the last /* On non-E500 family PPC32 we determine the size by picking the last
* register we need, but on E500 we skip sections so we list what we * register we need, but on E500 we skip sections so we list what we
* need to store, and add it up. */ * need to store, and add it up. */
#ifndef CONFIG_E500 #ifndef CONFIG_PPC_E500
#define MAXREG (PT_FPSCR+1) #define MAXREG (PT_FPSCR+1)
#else #else
/* 32 GPRs (8 bytes), nip, msr, ccr, link, ctr, xer, acc (8 bytes), spefscr*/ /* 32 GPRs (8 bytes), nip, msr, ccr, link, ctr, xer, acc (8 bytes), spefscr*/

View File

@ -162,7 +162,7 @@ enum {
#elif defined(CONFIG_44x) #elif defined(CONFIG_44x)
MMU_FTR_TYPE_44x | MMU_FTR_TYPE_44x |
#endif #endif
#ifdef CONFIG_E500 #ifdef CONFIG_PPC_E500
MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | MMU_FTR_USE_TLBILX | MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | MMU_FTR_USE_TLBILX |
#endif #endif
#ifdef CONFIG_PPC_BOOK3S_32 #ifdef CONFIG_PPC_BOOK3S_32
@ -211,7 +211,7 @@ enum {
#elif defined(CONFIG_44x) #elif defined(CONFIG_44x)
#define MMU_FTRS_ALWAYS MMU_FTR_TYPE_44x #define MMU_FTRS_ALWAYS MMU_FTR_TYPE_44x
#endif #endif
#ifdef CONFIG_E500 #ifdef CONFIG_PPC_E500
#define MMU_FTRS_ALWAYS MMU_FTR_TYPE_FSL_E #define MMU_FTRS_ALWAYS MMU_FTR_TYPE_FSL_E
#endif #endif

View File

@ -246,7 +246,7 @@
#define PPC47x_MCSR_FPR 0x00800000 /* FPR parity error */ #define PPC47x_MCSR_FPR 0x00800000 /* FPR parity error */
#define PPC47x_MCSR_IPR 0x00400000 /* Imprecise Machine Check Exception */ #define PPC47x_MCSR_IPR 0x00400000 /* Imprecise Machine Check Exception */
#ifdef CONFIG_E500 #ifdef CONFIG_PPC_E500
/* All e500 */ /* All e500 */
#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ #define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */ #define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
@ -282,7 +282,7 @@
#endif #endif
/* Bit definitions for the HID1 */ /* Bit definitions for the HID1 */
#ifdef CONFIG_E500 #ifdef CONFIG_PPC_E500
/* e500v1/v2 */ /* e500v1/v2 */
#define HID1_PLL_CFG_MASK 0xfc000000 /* PLL_CFG input pins */ #define HID1_PLL_CFG_MASK 0xfc000000 /* PLL_CFG input pins */
#define HID1_RFXE 0x00020000 /* Read fault exception enable */ #define HID1_RFXE 0x00020000 /* Read fault exception enable */
@ -545,7 +545,7 @@
#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
#define TCR_ARE 0x00400000 /* Auto Reload Enable */ #define TCR_ARE 0x00400000 /* Auto Reload Enable */
#ifdef CONFIG_E500 #ifdef CONFIG_PPC_E500
#define TCR_GET_WP(tcr) ((((tcr) & 0xC0000000) >> 30) | \ #define TCR_GET_WP(tcr) ((((tcr) & 0xC0000000) >> 30) | \
(((tcr) & 0x1E0000) >> 15)) (((tcr) & 0x1E0000) >> 15))
#else #else

View File

@ -44,7 +44,7 @@ static inline void ppc_after_tlbiel_barrier(void)
#if defined(__powerpc64__) #if defined(__powerpc64__)
# define LWSYNC lwsync # define LWSYNC lwsync
#elif defined(CONFIG_E500) #elif defined(CONFIG_PPC_E500)
# define LWSYNC \ # define LWSYNC \
START_LWSYNC_SECTION(96); \ START_LWSYNC_SECTION(96); \
sync; \ sync; \

View File

@ -12,7 +12,7 @@
* We use __powerpc64__ here because we want the compat VDSO to use the 32-bit * We use __powerpc64__ here because we want the compat VDSO to use the 32-bit
* version below in the else case of the ifdef. * version below in the else case of the ifdef.
*/ */
#if defined(__powerpc64__) && (defined(CONFIG_PPC_CELL) || defined(CONFIG_E500)) #if defined(__powerpc64__) && (defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_E500))
#define mftb() ({unsigned long rval; \ #define mftb() ({unsigned long rval; \
asm volatile( \ asm volatile( \
"90: mfspr %0, %2;\n" \ "90: mfspr %0, %2;\n" \

View File

@ -101,7 +101,7 @@ obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
obj-$(CONFIG_FA_DUMP) += fadump.o obj-$(CONFIG_FA_DUMP) += fadump.o
obj-$(CONFIG_PRESERVE_FA_DUMP) += fadump.o obj-$(CONFIG_PRESERVE_FA_DUMP) += fadump.o
ifdef CONFIG_PPC32 ifdef CONFIG_PPC32
obj-$(CONFIG_E500) += idle_e500.o obj-$(CONFIG_PPC_E500) += idle_e500.o
endif endif
obj-$(CONFIG_PPC_BOOK3S_32) += idle_6xx.o l2cr_6xx.o cpu_setup_6xx.o obj-$(CONFIG_PPC_BOOK3S_32) += idle_6xx.o l2cr_6xx.o cpu_setup_6xx.o
obj-$(CONFIG_TAU) += tau_6xx.o obj-$(CONFIG_TAU) += tau_6xx.o

View File

@ -108,7 +108,7 @@ _GLOBAL(__setup_cpu_e6500)
#endif /* CONFIG_PPC_E500MC */ #endif /* CONFIG_PPC_E500MC */
#ifdef CONFIG_PPC32 #ifdef CONFIG_PPC32
#ifdef CONFIG_E500 #ifdef CONFIG_PPC_E500
#ifndef CONFIG_PPC_E500MC #ifndef CONFIG_PPC_E500MC
_GLOBAL(__setup_cpu_e500v1) _GLOBAL(__setup_cpu_e500v1)
_GLOBAL(__setup_cpu_e500v2) _GLOBAL(__setup_cpu_e500v2)
@ -156,7 +156,7 @@ _GLOBAL(__setup_cpu_e5500)
mtlr r5 mtlr r5
blr blr
#endif /* CONFIG_PPC_E500MC */ #endif /* CONFIG_PPC_E500MC */
#endif /* CONFIG_E500 */ #endif /* CONFIG_PPC_E500 */
#endif /* CONFIG_PPC32 */ #endif /* CONFIG_PPC32 */
#ifdef CONFIG_PPC_BOOK3E_64 #ifdef CONFIG_PPC_BOOK3E_64

View File

@ -49,7 +49,7 @@
*/ */
.align 12 .align 12
#if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500) #if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_E500)
.globl prepare_transfer_to_handler .globl prepare_transfer_to_handler
prepare_transfer_to_handler: prepare_transfer_to_handler:
/* if from kernel, check interrupted DOZE/NAP mode */ /* if from kernel, check interrupted DOZE/NAP mode */
@ -71,7 +71,7 @@ prepare_transfer_to_handler:
lwz r2, GPR2(r11) lwz r2, GPR2(r11)
b fast_exception_return b fast_exception_return
_ASM_NOKPROBE_SYMBOL(prepare_transfer_to_handler) _ASM_NOKPROBE_SYMBOL(prepare_transfer_to_handler)
#endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_E500 */ #endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_PPC_E500 */
#if defined(CONFIG_PPC_KUEP) && defined(CONFIG_PPC_BOOK3S_32) #if defined(CONFIG_PPC_KUEP) && defined(CONFIG_PPC_BOOK3S_32)
.globl __kuep_lock .globl __kuep_lock

View File

@ -912,7 +912,7 @@ get_phys_addr:
* Global functions * Global functions
*/ */
#ifdef CONFIG_E500 #ifdef CONFIG_PPC_E500
#ifndef CONFIG_PPC_E500MC #ifndef CONFIG_PPC_E500MC
/* Adjust or setup IVORs for e500v1/v2 */ /* Adjust or setup IVORs for e500v1/v2 */
_GLOBAL(__setup_e500_ivors) _GLOBAL(__setup_e500_ivors)
@ -955,7 +955,7 @@ _GLOBAL(__setup_ehv_ivors)
sync sync
blr blr
#endif /* CONFIG_PPC_E500MC */ #endif /* CONFIG_PPC_E500MC */
#endif /* CONFIG_E500 */ #endif /* CONFIG_PPC_E500 */
#ifdef CONFIG_SPE #ifdef CONFIG_SPE
/* /*

View File

@ -103,7 +103,7 @@ END_BTB_FLUSH_SECTION
.endm .endm
.macro prepare_transfer_to_handler .macro prepare_transfer_to_handler
#ifdef CONFIG_E500 #ifdef CONFIG_PPC_E500
andi. r12,r9,MSR_PR andi. r12,r9,MSR_PR
bne 777f bne 777f
bl prepare_transfer_to_handler bl prepare_transfer_to_handler

View File

@ -207,7 +207,7 @@ void __init setup_power_save(void)
ppc_md.power_save = ppc6xx_idle; ppc_md.power_save = ppc6xx_idle;
#endif #endif
#ifdef CONFIG_E500 #ifdef CONFIG_PPC_E500
if (cpu_has_feature(CPU_FTR_CAN_DOZE) || if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
cpu_has_feature(CPU_FTR_CAN_NAP)) cpu_has_feature(CPU_FTR_CAN_NAP))
ppc_md.power_save = e500_idle; ppc_md.power_save = e500_idle;

View File

@ -600,7 +600,7 @@ static inline int check_io_access(struct pt_regs *regs)
#define inst_length(reason) (((reason) & REASON_PREFIXED) ? 8 : 4) #define inst_length(reason) (((reason) & REASON_PREFIXED) ? 8 : 4)
#if defined(CONFIG_E500) #if defined(CONFIG_PPC_E500)
int machine_check_e500mc(struct pt_regs *regs) int machine_check_e500mc(struct pt_regs *regs)
{ {
unsigned long mcsr = mfspr(SPRN_MCSR); unsigned long mcsr = mfspr(SPRN_MCSR);

View File

@ -189,7 +189,7 @@ config KVM_EXIT_TIMING
config KVM_E500V2 config KVM_E500V2
bool "KVM support for PowerPC E500v2 processors" bool "KVM support for PowerPC E500v2 processors"
depends on E500 && !PPC_E500MC depends on PPC_E500 && !PPC_E500MC
select KVM select KVM
select KVM_MMIO select KVM_MMIO
select MMU_NOTIFIER select MMU_NOTIFIER
@ -220,7 +220,7 @@ config KVM_E500MC
config KVM_MPIC config KVM_MPIC
bool "KVM in-kernel MPIC emulation" bool "KVM in-kernel MPIC emulation"
depends on KVM && E500 depends on KVM && PPC_E500
select HAVE_KVM_IRQCHIP select HAVE_KVM_IRQCHIP
select HAVE_KVM_IRQFD select HAVE_KVM_IRQFD
select HAVE_KVM_IRQ_ROUTING select HAVE_KVM_IRQ_ROUTING

View File

@ -33,7 +33,7 @@ config PPC_BOOK3S_32
config PPC_85xx config PPC_85xx
bool "Freescale 85xx" bool "Freescale 85xx"
select E500 select PPC_E500
config PPC_8xx config PPC_8xx
bool "Freescale 8xx" bool "Freescale 8xx"
@ -108,7 +108,7 @@ config PPC_BOOK3S_64
config PPC_BOOK3E_64 config PPC_BOOK3E_64
bool "Embedded processors" bool "Embedded processors"
select PPC_FSL_BOOK3E select PPC_FSL_BOOK3E
select E500 select PPC_E500
select PPC_E500MC select PPC_E500MC
select PPC_FPU # Make it a choice ? select PPC_FPU # Make it a choice ?
select PPC_SMP_MUXED_IPI select PPC_SMP_MUXED_IPI
@ -175,11 +175,11 @@ config POWER9_CPU
config E5500_CPU config E5500_CPU
bool "Freescale e5500" bool "Freescale e5500"
depends on PPC64 && E500 depends on PPC64 && PPC_E500
config E6500_CPU config E6500_CPU
bool "Freescale e6500" bool "Freescale e6500"
depends on PPC64 && E500 depends on PPC64 && PPC_E500
config 405_CPU config 405_CPU
bool "40x family" bool "40x family"
@ -257,7 +257,7 @@ config PPC_BOOK3S
def_bool y def_bool y
depends on PPC_BOOK3S_32 || PPC_BOOK3S_64 depends on PPC_BOOK3S_32 || PPC_BOOK3S_64
config E500 config PPC_E500
select FSL_EMB_PERFMON select FSL_EMB_PERFMON
select PPC_FSL_BOOK3E select PPC_FSL_BOOK3E
bool bool
@ -266,7 +266,7 @@ config PPC_E500MC
bool "e500mc Support" bool "e500mc Support"
select PPC_FPU select PPC_FPU
select COMMON_CLK select COMMON_CLK
depends on E500 depends on PPC_E500
help help
This must be enabled for running on e500mc (and derivatives This must be enabled for running on e500mc (and derivatives
such as e5500/e6500), and must be disabled for running on such as e5500/e6500), and must be disabled for running on
@ -289,7 +289,7 @@ config PPC_FPU
config FSL_EMB_PERFMON config FSL_EMB_PERFMON
bool "Freescale Embedded Perfmon" bool "Freescale Embedded Perfmon"
depends on E500 || PPC_83xx depends on PPC_E500 || PPC_83xx
help help
This is the Performance Monitor support found on the e500 core This is the Performance Monitor support found on the e500 core
and some e300 cores (c3 and c4). Select this only if your and some e300 cores (c3 and c4). Select this only if your
@ -302,7 +302,7 @@ config FSL_EMB_PERF_EVENT
config FSL_EMB_PERF_EVENT_E500 config FSL_EMB_PERF_EVENT_E500
bool bool
depends on FSL_EMB_PERF_EVENT && E500 depends on FSL_EMB_PERF_EVENT && PPC_E500
default y default y
config 4xx config 4xx
@ -312,7 +312,7 @@ config 4xx
config BOOKE config BOOKE
bool bool
depends on E500 || 44x || PPC_BOOK3E_64 depends on PPC_E500 || 44x || PPC_BOOK3E_64
default y default y
config BOOKE_OR_40x config BOOKE_OR_40x
@ -332,12 +332,12 @@ config PPC_FSL_BOOK3E
config PTE_64BIT config PTE_64BIT
bool bool
depends on 44x || E500 || PPC_86xx depends on 44x || PPC_E500 || PPC_86xx
default y if PHYS_64BIT default y if PHYS_64BIT
config PHYS_64BIT config PHYS_64BIT
bool 'Large physical address support' if E500 || PPC_86xx bool 'Large physical address support' if PPC_E500 || PPC_86xx
depends on (44x || E500 || PPC_86xx) && !PPC_83xx && !PPC_82xx depends on (44x || PPC_E500 || PPC_86xx) && !PPC_83xx && !PPC_82xx
select PHYS_ADDR_T_64BIT select PHYS_ADDR_T_64BIT
help help
This option enables kernel support for larger than 32-bit physical This option enables kernel support for larger than 32-bit physical
@ -384,7 +384,7 @@ config VSX
config SPE_POSSIBLE config SPE_POSSIBLE
def_bool y def_bool y
depends on E500 && !PPC_E500MC depends on PPC_E500 && !PPC_E500MC
config SPE config SPE
bool "SPE Support" bool "SPE Support"

View File

@ -943,7 +943,7 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose)
return 0; return 0;
} }
#ifdef CONFIG_E500 #ifdef CONFIG_PPC_E500
static int mcheck_handle_load(struct pt_regs *regs, u32 inst) static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
{ {
unsigned int rd, ra, rb, d; unsigned int rd, ra, rb, d;

View File

@ -98,7 +98,7 @@ resource_size_t rio_law_start;
struct fsl_rio_dbell *dbell; struct fsl_rio_dbell *dbell;
struct fsl_rio_pw *pw; struct fsl_rio_pw *pw;
#ifdef CONFIG_E500 #ifdef CONFIG_PPC_E500
int fsl_rio_mcheck_exception(struct pt_regs *regs) int fsl_rio_mcheck_exception(struct pt_regs *regs)
{ {
const struct exception_table_entry *entry; const struct exception_table_entry *entry;