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powerpc: Change CONFIG_E500 to CONFIG_PPC_E500
It will be used outside arch/powerpc, make it clear its a powerpc configuration item. And we already have CONFIG_PPC_E500MC, so that will make it more consistent. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/e63b22083c11c4300f4a82d3123a46e5fdd54fa6.1663606876.git.christophe.leroy@csgroup.eu
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@ -210,7 +210,7 @@ KBUILD_CFLAGS += $(call cc-option,-mno-string)
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cpu-as-$(CONFIG_40x) += -Wa,-m405
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cpu-as-$(CONFIG_44x) += -Wa,-m440
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cpu-as-$(CONFIG_ALTIVEC) += $(call as-option,-Wa$(comma)-maltivec)
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cpu-as-$(CONFIG_E500) += -Wa,-me500
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cpu-as-$(CONFIG_PPC_E500) += -Wa,-me500
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# When using '-many -mpower4' gas will first try and find a matching power4
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# mnemonic and failing that it will allow any valid mnemonic that GAS knows
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@ -510,7 +510,7 @@ enum {
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#elif defined(CONFIG_44x)
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CPU_FTRS_44X | CPU_FTRS_440x6 |
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#endif
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#ifdef CONFIG_E500
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#ifdef CONFIG_PPC_E500
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CPU_FTRS_E500 | CPU_FTRS_E500_2 |
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#endif
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#ifdef CONFIG_PPC_E500MC
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@ -584,7 +584,7 @@ enum {
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#elif defined(CONFIG_44x)
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CPU_FTRS_44X & CPU_FTRS_440x6 &
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#endif
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#ifdef CONFIG_E500
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#ifdef CONFIG_PPC_E500
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CPU_FTRS_E500 & CPU_FTRS_E500_2 &
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#endif
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#ifdef CONFIG_PPC_E500MC
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@ -52,7 +52,7 @@ static inline void arch_kgdb_breakpoint(void)
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/* On non-E500 family PPC32 we determine the size by picking the last
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* register we need, but on E500 we skip sections so we list what we
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* need to store, and add it up. */
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#ifndef CONFIG_E500
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#ifndef CONFIG_PPC_E500
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#define MAXREG (PT_FPSCR+1)
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#else
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/* 32 GPRs (8 bytes), nip, msr, ccr, link, ctr, xer, acc (8 bytes), spefscr*/
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@ -162,7 +162,7 @@ enum {
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#elif defined(CONFIG_44x)
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MMU_FTR_TYPE_44x |
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#endif
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#ifdef CONFIG_E500
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#ifdef CONFIG_PPC_E500
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MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | MMU_FTR_USE_TLBILX |
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#endif
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#ifdef CONFIG_PPC_BOOK3S_32
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@ -211,7 +211,7 @@ enum {
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#elif defined(CONFIG_44x)
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#define MMU_FTRS_ALWAYS MMU_FTR_TYPE_44x
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#endif
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#ifdef CONFIG_E500
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#ifdef CONFIG_PPC_E500
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#define MMU_FTRS_ALWAYS MMU_FTR_TYPE_FSL_E
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#endif
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@ -246,7 +246,7 @@
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#define PPC47x_MCSR_FPR 0x00800000 /* FPR parity error */
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#define PPC47x_MCSR_IPR 0x00400000 /* Imprecise Machine Check Exception */
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#ifdef CONFIG_E500
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#ifdef CONFIG_PPC_E500
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/* All e500 */
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#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
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#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
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@ -282,7 +282,7 @@
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#endif
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/* Bit definitions for the HID1 */
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#ifdef CONFIG_E500
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#ifdef CONFIG_PPC_E500
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/* e500v1/v2 */
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#define HID1_PLL_CFG_MASK 0xfc000000 /* PLL_CFG input pins */
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#define HID1_RFXE 0x00020000 /* Read fault exception enable */
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@ -545,7 +545,7 @@
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#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
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#define TCR_ARE 0x00400000 /* Auto Reload Enable */
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#ifdef CONFIG_E500
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#ifdef CONFIG_PPC_E500
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#define TCR_GET_WP(tcr) ((((tcr) & 0xC0000000) >> 30) | \
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(((tcr) & 0x1E0000) >> 15))
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#else
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@ -44,7 +44,7 @@ static inline void ppc_after_tlbiel_barrier(void)
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#if defined(__powerpc64__)
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# define LWSYNC lwsync
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#elif defined(CONFIG_E500)
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#elif defined(CONFIG_PPC_E500)
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# define LWSYNC \
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START_LWSYNC_SECTION(96); \
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sync; \
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@ -12,7 +12,7 @@
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* We use __powerpc64__ here because we want the compat VDSO to use the 32-bit
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* version below in the else case of the ifdef.
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*/
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#if defined(__powerpc64__) && (defined(CONFIG_PPC_CELL) || defined(CONFIG_E500))
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#if defined(__powerpc64__) && (defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_E500))
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#define mftb() ({unsigned long rval; \
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asm volatile( \
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"90: mfspr %0, %2;\n" \
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@ -101,7 +101,7 @@ obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
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obj-$(CONFIG_FA_DUMP) += fadump.o
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obj-$(CONFIG_PRESERVE_FA_DUMP) += fadump.o
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ifdef CONFIG_PPC32
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obj-$(CONFIG_E500) += idle_e500.o
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obj-$(CONFIG_PPC_E500) += idle_e500.o
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endif
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obj-$(CONFIG_PPC_BOOK3S_32) += idle_6xx.o l2cr_6xx.o cpu_setup_6xx.o
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obj-$(CONFIG_TAU) += tau_6xx.o
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@ -108,7 +108,7 @@ _GLOBAL(__setup_cpu_e6500)
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#endif /* CONFIG_PPC_E500MC */
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#ifdef CONFIG_PPC32
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#ifdef CONFIG_E500
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#ifdef CONFIG_PPC_E500
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#ifndef CONFIG_PPC_E500MC
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_GLOBAL(__setup_cpu_e500v1)
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_GLOBAL(__setup_cpu_e500v2)
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@ -156,7 +156,7 @@ _GLOBAL(__setup_cpu_e5500)
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mtlr r5
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blr
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#endif /* CONFIG_PPC_E500MC */
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#endif /* CONFIG_E500 */
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#endif /* CONFIG_PPC_E500 */
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#endif /* CONFIG_PPC32 */
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#ifdef CONFIG_PPC_BOOK3E_64
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@ -49,7 +49,7 @@
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*/
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.align 12
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#if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500)
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#if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_E500)
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.globl prepare_transfer_to_handler
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prepare_transfer_to_handler:
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/* if from kernel, check interrupted DOZE/NAP mode */
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@ -71,7 +71,7 @@ prepare_transfer_to_handler:
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lwz r2, GPR2(r11)
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b fast_exception_return
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_ASM_NOKPROBE_SYMBOL(prepare_transfer_to_handler)
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#endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_E500 */
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#endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_PPC_E500 */
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#if defined(CONFIG_PPC_KUEP) && defined(CONFIG_PPC_BOOK3S_32)
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.globl __kuep_lock
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@ -912,7 +912,7 @@ get_phys_addr:
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* Global functions
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*/
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#ifdef CONFIG_E500
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#ifdef CONFIG_PPC_E500
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#ifndef CONFIG_PPC_E500MC
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/* Adjust or setup IVORs for e500v1/v2 */
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_GLOBAL(__setup_e500_ivors)
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@ -955,7 +955,7 @@ _GLOBAL(__setup_ehv_ivors)
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sync
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blr
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#endif /* CONFIG_PPC_E500MC */
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#endif /* CONFIG_E500 */
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#endif /* CONFIG_PPC_E500 */
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#ifdef CONFIG_SPE
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/*
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@ -103,7 +103,7 @@ END_BTB_FLUSH_SECTION
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.endm
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.macro prepare_transfer_to_handler
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#ifdef CONFIG_E500
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#ifdef CONFIG_PPC_E500
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andi. r12,r9,MSR_PR
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bne 777f
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bl prepare_transfer_to_handler
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@ -207,7 +207,7 @@ void __init setup_power_save(void)
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ppc_md.power_save = ppc6xx_idle;
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#endif
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#ifdef CONFIG_E500
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#ifdef CONFIG_PPC_E500
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if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
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cpu_has_feature(CPU_FTR_CAN_NAP))
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ppc_md.power_save = e500_idle;
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@ -600,7 +600,7 @@ static inline int check_io_access(struct pt_regs *regs)
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#define inst_length(reason) (((reason) & REASON_PREFIXED) ? 8 : 4)
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#if defined(CONFIG_E500)
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#if defined(CONFIG_PPC_E500)
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int machine_check_e500mc(struct pt_regs *regs)
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{
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unsigned long mcsr = mfspr(SPRN_MCSR);
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@ -189,7 +189,7 @@ config KVM_EXIT_TIMING
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config KVM_E500V2
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bool "KVM support for PowerPC E500v2 processors"
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depends on E500 && !PPC_E500MC
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depends on PPC_E500 && !PPC_E500MC
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select KVM
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select KVM_MMIO
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select MMU_NOTIFIER
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@ -220,7 +220,7 @@ config KVM_E500MC
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config KVM_MPIC
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bool "KVM in-kernel MPIC emulation"
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depends on KVM && E500
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depends on KVM && PPC_E500
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select HAVE_KVM_IRQCHIP
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select HAVE_KVM_IRQFD
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select HAVE_KVM_IRQ_ROUTING
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@ -33,7 +33,7 @@ config PPC_BOOK3S_32
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config PPC_85xx
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bool "Freescale 85xx"
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select E500
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select PPC_E500
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config PPC_8xx
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bool "Freescale 8xx"
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@ -108,7 +108,7 @@ config PPC_BOOK3S_64
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config PPC_BOOK3E_64
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bool "Embedded processors"
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select PPC_FSL_BOOK3E
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select E500
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select PPC_E500
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select PPC_E500MC
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select PPC_FPU # Make it a choice ?
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select PPC_SMP_MUXED_IPI
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@ -175,11 +175,11 @@ config POWER9_CPU
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config E5500_CPU
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bool "Freescale e5500"
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depends on PPC64 && E500
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depends on PPC64 && PPC_E500
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config E6500_CPU
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bool "Freescale e6500"
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depends on PPC64 && E500
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depends on PPC64 && PPC_E500
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config 405_CPU
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bool "40x family"
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@ -257,7 +257,7 @@ config PPC_BOOK3S
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def_bool y
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depends on PPC_BOOK3S_32 || PPC_BOOK3S_64
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config E500
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config PPC_E500
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select FSL_EMB_PERFMON
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select PPC_FSL_BOOK3E
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bool
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@ -266,7 +266,7 @@ config PPC_E500MC
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bool "e500mc Support"
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select PPC_FPU
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select COMMON_CLK
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depends on E500
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depends on PPC_E500
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help
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This must be enabled for running on e500mc (and derivatives
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such as e5500/e6500), and must be disabled for running on
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@ -289,7 +289,7 @@ config PPC_FPU
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config FSL_EMB_PERFMON
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bool "Freescale Embedded Perfmon"
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depends on E500 || PPC_83xx
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depends on PPC_E500 || PPC_83xx
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help
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This is the Performance Monitor support found on the e500 core
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and some e300 cores (c3 and c4). Select this only if your
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@ -302,7 +302,7 @@ config FSL_EMB_PERF_EVENT
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config FSL_EMB_PERF_EVENT_E500
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bool
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depends on FSL_EMB_PERF_EVENT && E500
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depends on FSL_EMB_PERF_EVENT && PPC_E500
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default y
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config 4xx
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@ -312,7 +312,7 @@ config 4xx
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config BOOKE
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bool
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depends on E500 || 44x || PPC_BOOK3E_64
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depends on PPC_E500 || 44x || PPC_BOOK3E_64
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default y
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config BOOKE_OR_40x
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@ -332,12 +332,12 @@ config PPC_FSL_BOOK3E
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config PTE_64BIT
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bool
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depends on 44x || E500 || PPC_86xx
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depends on 44x || PPC_E500 || PPC_86xx
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default y if PHYS_64BIT
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config PHYS_64BIT
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bool 'Large physical address support' if E500 || PPC_86xx
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depends on (44x || E500 || PPC_86xx) && !PPC_83xx && !PPC_82xx
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bool 'Large physical address support' if PPC_E500 || PPC_86xx
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depends on (44x || PPC_E500 || PPC_86xx) && !PPC_83xx && !PPC_82xx
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select PHYS_ADDR_T_64BIT
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help
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This option enables kernel support for larger than 32-bit physical
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@ -384,7 +384,7 @@ config VSX
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config SPE_POSSIBLE
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def_bool y
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depends on E500 && !PPC_E500MC
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depends on PPC_E500 && !PPC_E500MC
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config SPE
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bool "SPE Support"
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@ -943,7 +943,7 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose)
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return 0;
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}
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#ifdef CONFIG_E500
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#ifdef CONFIG_PPC_E500
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static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
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{
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unsigned int rd, ra, rb, d;
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@ -98,7 +98,7 @@ resource_size_t rio_law_start;
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struct fsl_rio_dbell *dbell;
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struct fsl_rio_pw *pw;
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#ifdef CONFIG_E500
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#ifdef CONFIG_PPC_E500
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int fsl_rio_mcheck_exception(struct pt_regs *regs)
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{
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const struct exception_table_entry *entry;
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