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stmmac: fix Transmit FIFO flush operation
Fix the Transmit FIFO flush operation; it was disabled while reworking the descriptor structures. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -244,3 +244,4 @@ extern void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6],
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unsigned int high, unsigned int low);
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extern void stmmac_get_mac_addr(unsigned long ioaddr, unsigned char *addr,
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unsigned int high, unsigned int low);
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extern void dwmac_dma_flush_tx_fifo(unsigned long ioaddr);
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@ -172,7 +172,6 @@ enum rfd {
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deac_full_minus_4 = 0x00401800,
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};
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#define DMA_CONTROL_TSF 0x00200000 /* Transmit Store and Forward */
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#define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */
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enum ttc_control {
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DMA_CONTROL_TTC_64 = 0x00000000,
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@ -58,15 +58,6 @@ static int dwmac1000_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx,
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return 0;
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}
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/* Transmit FIFO flush operation */
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static void dwmac1000_flush_tx_fifo(unsigned long ioaddr)
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{
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u32 csr6 = readl(ioaddr + DMA_CONTROL);
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writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
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do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));
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}
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static void dwmac1000_dma_operation_mode(unsigned long ioaddr, int txmode,
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int rxmode)
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{
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@ -95,6 +95,7 @@
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#define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */
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#define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
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#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
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#define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */
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extern void dwmac_enable_dma_transmission(unsigned long ioaddr);
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extern void dwmac_enable_dma_irq(unsigned long ioaddr);
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@ -227,6 +227,13 @@ int dwmac_dma_interrupt(unsigned long ioaddr,
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return ret;
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}
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void dwmac_dma_flush_tx_fifo(unsigned long ioaddr)
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{
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u32 csr6 = readl(ioaddr + DMA_CONTROL);
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writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
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do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));
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}
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void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6],
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unsigned int high, unsigned int low)
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@ -40,7 +40,7 @@ static int enh_desc_get_tx_status(void *data, struct stmmac_extra_stats *x,
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if (unlikely(p->des01.etx.frame_flushed)) {
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CHIP_DBG(KERN_ERR "\tframe_flushed error\n");
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x->tx_frame_flushed++;
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/*enh_desc_flush_tx_fifo(ioaddr);*/
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dwmac_dma_flush_tx_fifo(ioaddr);
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}
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if (unlikely(p->des01.etx.loss_carrier)) {
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@ -68,7 +68,7 @@ static int enh_desc_get_tx_status(void *data, struct stmmac_extra_stats *x,
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if (unlikely(p->des01.etx.underflow_error)) {
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CHIP_DBG(KERN_ERR "\tunderflow error\n");
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/*enh_desc_flush_tx_fifo(ioaddr);*/
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dwmac_dma_flush_tx_fifo(ioaddr);
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x->tx_underflow++;
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}
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@ -80,7 +80,7 @@ static int enh_desc_get_tx_status(void *data, struct stmmac_extra_stats *x,
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if (unlikely(p->des01.etx.payload_error)) {
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CHIP_DBG(KERN_ERR "\tAddr/Payload csum error\n");
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x->tx_payload_error++;
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/*enh_desc_flush_tx_fifo(ioaddr);*/
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dwmac_dma_flush_tx_fifo(ioaddr);
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}
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ret = -1;
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