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MIPS: perf: Allow for more perf events

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In mipsxx_pmu_map_raw_event(), set event_id to base_id after the cpu
type conditional code to allow that code to override the base_id to use
more bits from the config and a higher bit for parity.

This will allow cores with up to 512 events between all even/odd
counters (an 8-bit event id) such as P5600 to use bit 8 for parity.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7243/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
James Hogan 2014-07-04 11:08:56 +01:00 committed by Ralf Baechle
parent 9f07925c43
commit 67dca66751
1 changed files with 13 additions and 8 deletions
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21
arch/mips/kernel/perf_event_mipsxx.c
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@ -1420,20 +1420,23 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
/*
* User can use 0-255 raw events, where 0-127 for the events of even
* counters, and 128-255 for odd counters. Note that bit 7 is used to
* indicate the parity. So, for example, when user wants to take the
* Event Num of 15 for odd counters (by referring to the user manual),
* then 128 needs to be added to 15 as the input for the event config,
* i.e., 143 (0x8F) to be used.
* For most cores the user can use 0-255 raw events, where 0-127 for the events
* of even counters, and 128-255 for odd counters. Note that bit 7 is used to
* indicate the even/odd bank selector. So, for example, when user wants to take
* the Event Num of 15 for odd counters (by referring to the user manual), then
* 128 needs to be added to 15 as the input for the event config, i.e., 143 (0x8F)
* to be used.
*
* Some newer cores have even more events, in which case the user can use raw
* events 0-511, where 0-255 are for the events of even counters, and 256-511
* are for odd counters, so bit 8 is used to indicate the even/odd bank selector.
*/
static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
{
/* currently most cores have 7-bit event numbers */
unsigned int raw_id = config & 0xff;
unsigned int base_id = raw_id & 0x7f;
raw_event.event_id = base_id;
switch (current_cpu_type()) {
case CPU_24K:
if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
@ -1523,6 +1526,8 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
}
raw_event.event_id = base_id;
return &raw_event;
}