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ASoC: mediatek: mt8195: add platform driver
This patch adds mt8195 platform and affiliated driver. Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20210819084144.18483-7-trevor.wu@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Trevor Wu
Mark Brown
parent
1f95c01911
commit
6746cc8582
@ -184,3 +184,12 @@ config SND_SOC_MT8192_MT6359_RT1015_RT5682
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with the MT6359 RT1015 RT5682 audio codec.
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Select Y if you have such device.
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If unsure select "N".
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config SND_SOC_MT8195
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tristate "ASoC support for Mediatek MT8195 chip"
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select SND_SOC_MEDIATEK
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help
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This adds ASoC platform driver support for Mediatek MT8195 chip
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that can be used with other codecs.
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Select Y if you have such device.
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If unsure select "N".
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@ -5,3 +5,4 @@ obj-$(CONFIG_SND_SOC_MT6797) += mt6797/
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obj-$(CONFIG_SND_SOC_MT8173) += mt8173/
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obj-$(CONFIG_SND_SOC_MT8183) += mt8183/
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obj-$(CONFIG_SND_SOC_MT8192) += mt8192/
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obj-$(CONFIG_SND_SOC_MT8195) += mt8195/
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12
sound/soc/mediatek/mt8195/Makefile
Normal file
12
sound/soc/mediatek/mt8195/Makefile
Normal file
@ -0,0 +1,12 @@
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# SPDX-License-Identifier: GPL-2.0
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# platform driver
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snd-soc-mt8195-afe-objs := \
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mt8195-audsys-clk.o \
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mt8195-afe-clk.o \
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mt8195-afe-pcm.o \
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mt8195-dai-adda.o \
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mt8195-dai-etdm.o \
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mt8195-dai-pcm.o
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obj-$(CONFIG_SND_SOC_MT8195) += snd-soc-mt8195-afe.o
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441
sound/soc/mediatek/mt8195/mt8195-afe-clk.c
Normal file
441
sound/soc/mediatek/mt8195/mt8195-afe-clk.c
Normal file
@ -0,0 +1,441 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* mt8195-afe-clk.c -- Mediatek 8195 afe clock ctrl
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*
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* Copyright (c) 2021 MediaTek Inc.
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* Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
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* Trevor Wu <trevor.wu@mediatek.com>
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*/
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#include <linux/clk.h>
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#include "mt8195-afe-common.h"
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#include "mt8195-afe-clk.h"
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#include "mt8195-reg.h"
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#include "mt8195-audsys-clk.h"
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static const char *aud_clks[MT8195_CLK_NUM] = {
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/* xtal */
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[MT8195_CLK_XTAL_26M] = "clk26m",
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/* divider */
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[MT8195_CLK_TOP_APLL1] = "apll1_ck",
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[MT8195_CLK_TOP_APLL2] = "apll2_ck",
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[MT8195_CLK_TOP_APLL12_DIV0] = "apll12_div0",
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[MT8195_CLK_TOP_APLL12_DIV1] = "apll12_div1",
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[MT8195_CLK_TOP_APLL12_DIV2] = "apll12_div2",
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[MT8195_CLK_TOP_APLL12_DIV3] = "apll12_div3",
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[MT8195_CLK_TOP_APLL12_DIV9] = "apll12_div9",
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/* mux */
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[MT8195_CLK_TOP_A1SYS_HP_SEL] = "a1sys_hp_sel",
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[MT8195_CLK_TOP_AUD_INTBUS_SEL] = "aud_intbus_sel",
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[MT8195_CLK_TOP_AUDIO_H_SEL] = "audio_h_sel",
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[MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "audio_local_bus_sel",
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[MT8195_CLK_TOP_DPTX_M_SEL] = "dptx_m_sel",
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[MT8195_CLK_TOP_I2SO1_M_SEL] = "i2so1_m_sel",
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[MT8195_CLK_TOP_I2SO2_M_SEL] = "i2so2_m_sel",
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[MT8195_CLK_TOP_I2SI1_M_SEL] = "i2si1_m_sel",
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[MT8195_CLK_TOP_I2SI2_M_SEL] = "i2si2_m_sel",
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/* clock gate */
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[MT8195_CLK_INFRA_AO_AUDIO_26M_B] = "infra_ao_audio_26m_b",
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[MT8195_CLK_SCP_ADSP_AUDIODSP] = "scp_adsp_audiodsp",
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/* afe clock gate */
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[MT8195_CLK_AUD_AFE] = "aud_afe",
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[MT8195_CLK_AUD_APLL] = "aud_apll",
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[MT8195_CLK_AUD_APLL2] = "aud_apll2",
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[MT8195_CLK_AUD_DAC] = "aud_dac",
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[MT8195_CLK_AUD_ADC] = "aud_adc",
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[MT8195_CLK_AUD_DAC_HIRES] = "aud_dac_hires",
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[MT8195_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp",
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[MT8195_CLK_AUD_ADC_HIRES] = "aud_adc_hires",
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[MT8195_CLK_AUD_ADDA6_ADC] = "aud_adda6_adc",
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[MT8195_CLK_AUD_ADDA6_ADC_HIRES] = "aud_adda6_adc_hires",
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[MT8195_CLK_AUD_I2SIN] = "aud_i2sin",
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[MT8195_CLK_AUD_TDM_IN] = "aud_tdm_in",
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[MT8195_CLK_AUD_I2S_OUT] = "aud_i2s_out",
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[MT8195_CLK_AUD_TDM_OUT] = "aud_tdm_out",
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[MT8195_CLK_AUD_HDMI_OUT] = "aud_hdmi_out",
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[MT8195_CLK_AUD_ASRC11] = "aud_asrc11",
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[MT8195_CLK_AUD_ASRC12] = "aud_asrc12",
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[MT8195_CLK_AUD_A1SYS] = "aud_a1sys",
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[MT8195_CLK_AUD_A2SYS] = "aud_a2sys",
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[MT8195_CLK_AUD_PCMIF] = "aud_pcmif",
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[MT8195_CLK_AUD_MEMIF_UL1] = "aud_memif_ul1",
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[MT8195_CLK_AUD_MEMIF_UL2] = "aud_memif_ul2",
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[MT8195_CLK_AUD_MEMIF_UL3] = "aud_memif_ul3",
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[MT8195_CLK_AUD_MEMIF_UL4] = "aud_memif_ul4",
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[MT8195_CLK_AUD_MEMIF_UL5] = "aud_memif_ul5",
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[MT8195_CLK_AUD_MEMIF_UL6] = "aud_memif_ul6",
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[MT8195_CLK_AUD_MEMIF_UL8] = "aud_memif_ul8",
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[MT8195_CLK_AUD_MEMIF_UL9] = "aud_memif_ul9",
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[MT8195_CLK_AUD_MEMIF_UL10] = "aud_memif_ul10",
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[MT8195_CLK_AUD_MEMIF_DL2] = "aud_memif_dl2",
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[MT8195_CLK_AUD_MEMIF_DL3] = "aud_memif_dl3",
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[MT8195_CLK_AUD_MEMIF_DL6] = "aud_memif_dl6",
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[MT8195_CLK_AUD_MEMIF_DL7] = "aud_memif_dl7",
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[MT8195_CLK_AUD_MEMIF_DL8] = "aud_memif_dl8",
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[MT8195_CLK_AUD_MEMIF_DL10] = "aud_memif_dl10",
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[MT8195_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11",
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};
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int mt8195_afe_get_mclk_source_clk_id(int sel)
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{
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switch (sel) {
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case MT8195_MCK_SEL_26M:
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return MT8195_CLK_XTAL_26M;
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case MT8195_MCK_SEL_APLL1:
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return MT8195_CLK_TOP_APLL1;
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case MT8195_MCK_SEL_APLL2:
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return MT8195_CLK_TOP_APLL2;
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default:
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return -EINVAL;
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}
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}
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int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll)
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{
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struct mt8195_afe_private *afe_priv = afe->platform_priv;
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int clk_id = mt8195_afe_get_mclk_source_clk_id(apll);
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if (clk_id < 0) {
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dev_dbg(afe->dev, "invalid clk id\n");
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return 0;
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}
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return clk_get_rate(afe_priv->clk[clk_id]);
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}
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int mt8195_afe_get_default_mclk_source_by_rate(int rate)
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{
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return ((rate % 8000) == 0) ?
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MT8195_MCK_SEL_APLL1 : MT8195_MCK_SEL_APLL2;
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}
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int mt8195_afe_init_clock(struct mtk_base_afe *afe)
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{
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struct mt8195_afe_private *afe_priv = afe->platform_priv;
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int i;
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mt8195_audsys_clk_register(afe);
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afe_priv->clk =
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devm_kcalloc(afe->dev, MT8195_CLK_NUM, sizeof(*afe_priv->clk),
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GFP_KERNEL);
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if (!afe_priv->clk)
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return -ENOMEM;
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for (i = 0; i < MT8195_CLK_NUM; i++) {
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afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
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if (IS_ERR(afe_priv->clk[i])) {
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dev_dbg(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
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__func__, aud_clks[i],
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PTR_ERR(afe_priv->clk[i]));
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return PTR_ERR(afe_priv->clk[i]);
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}
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}
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return 0;
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}
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void mt8195_afe_deinit_clock(struct mtk_base_afe *afe)
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{
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mt8195_audsys_clk_unregister(afe);
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}
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int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
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{
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int ret;
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if (clk) {
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ret = clk_prepare_enable(clk);
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if (ret) {
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dev_dbg(afe->dev, "%s(), failed to enable clk\n",
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__func__);
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return ret;
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}
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} else {
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dev_dbg(afe->dev, "NULL clk\n");
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(mt8195_afe_enable_clk);
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void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
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{
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if (clk)
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clk_disable_unprepare(clk);
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else
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dev_dbg(afe->dev, "NULL clk\n");
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}
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EXPORT_SYMBOL_GPL(mt8195_afe_disable_clk);
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int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk)
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{
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int ret;
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if (clk) {
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ret = clk_prepare(clk);
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if (ret) {
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dev_dbg(afe->dev, "%s(), failed to prepare clk\n",
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__func__);
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return ret;
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}
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} else {
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dev_dbg(afe->dev, "NULL clk\n");
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}
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return 0;
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}
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void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk)
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{
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if (clk)
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clk_unprepare(clk);
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else
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dev_dbg(afe->dev, "NULL clk\n");
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}
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int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk)
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{
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int ret;
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if (clk) {
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ret = clk_enable(clk);
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if (ret) {
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dev_dbg(afe->dev, "%s(), failed to clk enable\n",
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__func__);
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return ret;
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}
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} else {
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dev_dbg(afe->dev, "NULL clk\n");
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}
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return 0;
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}
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void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk)
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{
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if (clk)
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clk_disable(clk);
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else
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dev_dbg(afe->dev, "NULL clk\n");
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}
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int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
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unsigned int rate)
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{
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int ret;
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if (clk) {
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ret = clk_set_rate(clk, rate);
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if (ret) {
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dev_dbg(afe->dev, "%s(), failed to set clk rate\n",
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__func__);
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return ret;
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}
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}
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return 0;
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}
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int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
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struct clk *parent)
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{
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int ret;
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if (clk && parent) {
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ret = clk_set_parent(clk, parent);
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if (ret) {
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dev_dbg(afe->dev, "%s(), failed to set clk parent\n",
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__func__);
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return ret;
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}
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}
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return 0;
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}
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static unsigned int get_top_cg_reg(unsigned int cg_type)
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{
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switch (cg_type) {
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case MT8195_TOP_CG_A1SYS_TIMING:
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case MT8195_TOP_CG_A2SYS_TIMING:
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case MT8195_TOP_CG_26M_TIMING:
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return ASYS_TOP_CON;
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default:
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return 0;
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}
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}
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static unsigned int get_top_cg_mask(unsigned int cg_type)
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{
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switch (cg_type) {
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case MT8195_TOP_CG_A1SYS_TIMING:
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return ASYS_TOP_CON_A1SYS_TIMING_ON;
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case MT8195_TOP_CG_A2SYS_TIMING:
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return ASYS_TOP_CON_A2SYS_TIMING_ON;
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case MT8195_TOP_CG_26M_TIMING:
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return ASYS_TOP_CON_26M_TIMING_ON;
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default:
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return 0;
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}
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}
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static unsigned int get_top_cg_on_val(unsigned int cg_type)
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{
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switch (cg_type) {
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case MT8195_TOP_CG_A1SYS_TIMING:
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case MT8195_TOP_CG_A2SYS_TIMING:
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case MT8195_TOP_CG_26M_TIMING:
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return get_top_cg_mask(cg_type);
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default:
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return 0;
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}
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}
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static unsigned int get_top_cg_off_val(unsigned int cg_type)
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{
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switch (cg_type) {
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case MT8195_TOP_CG_A1SYS_TIMING:
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case MT8195_TOP_CG_A2SYS_TIMING:
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case MT8195_TOP_CG_26M_TIMING:
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return 0;
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default:
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return get_top_cg_mask(cg_type);
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}
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}
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static int mt8195_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
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{
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unsigned int reg = get_top_cg_reg(cg_type);
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unsigned int mask = get_top_cg_mask(cg_type);
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unsigned int val = get_top_cg_on_val(cg_type);
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regmap_update_bits(afe->regmap, reg, mask, val);
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return 0;
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}
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static int mt8195_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
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{
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unsigned int reg = get_top_cg_reg(cg_type);
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unsigned int mask = get_top_cg_mask(cg_type);
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unsigned int val = get_top_cg_off_val(cg_type);
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regmap_update_bits(afe->regmap, reg, mask, val);
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return 0;
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}
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int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
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{
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struct mt8195_afe_private *afe_priv = afe->platform_priv;
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int i;
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unsigned int clk_array[] = {
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MT8195_CLK_SCP_ADSP_AUDIODSP, /* bus clock for infra */
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MT8195_CLK_TOP_AUDIO_H_SEL, /* clock for ADSP bus */
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MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL, /* bus clock for DRAM access */
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MT8195_CLK_TOP_AUD_INTBUS_SEL, /* bus clock for AFE SRAM access */
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MT8195_CLK_INFRA_AO_AUDIO_26M_B, /* audio 26M clock */
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MT8195_CLK_AUD_AFE, /* AFE HW master switch */
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MT8195_CLK_AUD_A1SYS_HP, /* AFE HW clock*/
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MT8195_CLK_AUD_A1SYS, /* AFE HW clock */
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};
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for (i = 0; i < ARRAY_SIZE(clk_array); i++)
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mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]);
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return 0;
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}
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int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
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{
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struct mt8195_afe_private *afe_priv = afe->platform_priv;
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int i;
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unsigned int clk_array[] = {
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MT8195_CLK_AUD_A1SYS,
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MT8195_CLK_AUD_A1SYS_HP,
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MT8195_CLK_AUD_AFE,
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MT8195_CLK_INFRA_AO_AUDIO_26M_B,
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MT8195_CLK_TOP_AUD_INTBUS_SEL,
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MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL,
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MT8195_CLK_TOP_AUDIO_H_SEL,
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MT8195_CLK_SCP_ADSP_AUDIODSP,
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};
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for (i = 0; i < ARRAY_SIZE(clk_array); i++)
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mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]);
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return 0;
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}
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static int mt8195_afe_enable_afe_on(struct mtk_base_afe *afe)
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{
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regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
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return 0;
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}
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|
||||
static int mt8195_afe_disable_afe_on(struct mtk_base_afe *afe)
|
||||
{
|
||||
regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mt8195_afe_enable_timing_sys(struct mtk_base_afe *afe)
|
||||
{
|
||||
struct mt8195_afe_private *afe_priv = afe->platform_priv;
|
||||
int i;
|
||||
unsigned int clk_array[] = {
|
||||
MT8195_CLK_AUD_A1SYS,
|
||||
MT8195_CLK_AUD_A2SYS,
|
||||
};
|
||||
unsigned int cg_array[] = {
|
||||
MT8195_TOP_CG_A1SYS_TIMING,
|
||||
MT8195_TOP_CG_A2SYS_TIMING,
|
||||
MT8195_TOP_CG_26M_TIMING,
|
||||
};
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk_array); i++)
|
||||
mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cg_array); i++)
|
||||
mt8195_afe_enable_top_cg(afe, cg_array[i]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mt8195_afe_disable_timing_sys(struct mtk_base_afe *afe)
|
||||
{
|
||||
struct mt8195_afe_private *afe_priv = afe->platform_priv;
|
||||
int i;
|
||||
unsigned int clk_array[] = {
|
||||
MT8195_CLK_AUD_A2SYS,
|
||||
MT8195_CLK_AUD_A1SYS,
|
||||
};
|
||||
unsigned int cg_array[] = {
|
||||
MT8195_TOP_CG_26M_TIMING,
|
||||
MT8195_TOP_CG_A2SYS_TIMING,
|
||||
MT8195_TOP_CG_A1SYS_TIMING,
|
||||
};
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cg_array); i++)
|
||||
mt8195_afe_disable_top_cg(afe, cg_array[i]);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk_array); i++)
|
||||
mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe)
|
||||
{
|
||||
mt8195_afe_enable_timing_sys(afe);
|
||||
|
||||
mt8195_afe_enable_afe_on(afe);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe)
|
||||
{
|
||||
mt8195_afe_disable_afe_on(afe);
|
||||
|
||||
mt8195_afe_disable_timing_sys(afe);
|
||||
|
||||
return 0;
|
||||
}
|
||||
109
sound/soc/mediatek/mt8195/mt8195-afe-clk.h
Normal file
109
sound/soc/mediatek/mt8195/mt8195-afe-clk.h
Normal file
@ -0,0 +1,109 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* mt8195-afe-clk.h -- Mediatek 8195 afe clock ctrl definition
|
||||
*
|
||||
* Copyright (c) 2021 MediaTek Inc.
|
||||
* Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
|
||||
* Trevor Wu <trevor.wu@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef _MT8195_AFE_CLK_H_
|
||||
#define _MT8195_AFE_CLK_H_
|
||||
|
||||
enum {
|
||||
/* xtal */
|
||||
MT8195_CLK_XTAL_26M,
|
||||
/* divider */
|
||||
MT8195_CLK_TOP_APLL1,
|
||||
MT8195_CLK_TOP_APLL2,
|
||||
MT8195_CLK_TOP_APLL12_DIV0,
|
||||
MT8195_CLK_TOP_APLL12_DIV1,
|
||||
MT8195_CLK_TOP_APLL12_DIV2,
|
||||
MT8195_CLK_TOP_APLL12_DIV3,
|
||||
MT8195_CLK_TOP_APLL12_DIV9,
|
||||
/* mux */
|
||||
MT8195_CLK_TOP_A1SYS_HP_SEL,
|
||||
MT8195_CLK_TOP_AUD_INTBUS_SEL,
|
||||
MT8195_CLK_TOP_AUDIO_H_SEL,
|
||||
MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL,
|
||||
MT8195_CLK_TOP_DPTX_M_SEL,
|
||||
MT8195_CLK_TOP_I2SO1_M_SEL,
|
||||
MT8195_CLK_TOP_I2SO2_M_SEL,
|
||||
MT8195_CLK_TOP_I2SI1_M_SEL,
|
||||
MT8195_CLK_TOP_I2SI2_M_SEL,
|
||||
/* clock gate */
|
||||
MT8195_CLK_INFRA_AO_AUDIO_26M_B,
|
||||
MT8195_CLK_SCP_ADSP_AUDIODSP,
|
||||
MT8195_CLK_AUD_AFE,
|
||||
MT8195_CLK_AUD_APLL,
|
||||
MT8195_CLK_AUD_APLL2,
|
||||
MT8195_CLK_AUD_DAC,
|
||||
MT8195_CLK_AUD_ADC,
|
||||
MT8195_CLK_AUD_DAC_HIRES,
|
||||
MT8195_CLK_AUD_A1SYS_HP,
|
||||
MT8195_CLK_AUD_ADC_HIRES,
|
||||
MT8195_CLK_AUD_ADDA6_ADC,
|
||||
MT8195_CLK_AUD_ADDA6_ADC_HIRES,
|
||||
MT8195_CLK_AUD_I2SIN,
|
||||
MT8195_CLK_AUD_TDM_IN,
|
||||
MT8195_CLK_AUD_I2S_OUT,
|
||||
MT8195_CLK_AUD_TDM_OUT,
|
||||
MT8195_CLK_AUD_HDMI_OUT,
|
||||
MT8195_CLK_AUD_ASRC11,
|
||||
MT8195_CLK_AUD_ASRC12,
|
||||
MT8195_CLK_AUD_A1SYS,
|
||||
MT8195_CLK_AUD_A2SYS,
|
||||
MT8195_CLK_AUD_PCMIF,
|
||||
MT8195_CLK_AUD_MEMIF_UL1,
|
||||
MT8195_CLK_AUD_MEMIF_UL2,
|
||||
MT8195_CLK_AUD_MEMIF_UL3,
|
||||
MT8195_CLK_AUD_MEMIF_UL4,
|
||||
MT8195_CLK_AUD_MEMIF_UL5,
|
||||
MT8195_CLK_AUD_MEMIF_UL6,
|
||||
MT8195_CLK_AUD_MEMIF_UL8,
|
||||
MT8195_CLK_AUD_MEMIF_UL9,
|
||||
MT8195_CLK_AUD_MEMIF_UL10,
|
||||
MT8195_CLK_AUD_MEMIF_DL2,
|
||||
MT8195_CLK_AUD_MEMIF_DL3,
|
||||
MT8195_CLK_AUD_MEMIF_DL6,
|
||||
MT8195_CLK_AUD_MEMIF_DL7,
|
||||
MT8195_CLK_AUD_MEMIF_DL8,
|
||||
MT8195_CLK_AUD_MEMIF_DL10,
|
||||
MT8195_CLK_AUD_MEMIF_DL11,
|
||||
MT8195_CLK_NUM,
|
||||
};
|
||||
|
||||
enum {
|
||||
MT8195_MCK_SEL_26M,
|
||||
MT8195_MCK_SEL_APLL1,
|
||||
MT8195_MCK_SEL_APLL2,
|
||||
MT8195_MCK_SEL_APLL3,
|
||||
MT8195_MCK_SEL_APLL4,
|
||||
MT8195_MCK_SEL_APLL5,
|
||||
MT8195_MCK_SEL_HDMIRX_APLL,
|
||||
MT8195_MCK_SEL_NUM,
|
||||
};
|
||||
|
||||
struct mtk_base_afe;
|
||||
|
||||
int mt8195_afe_get_mclk_source_clk_id(int sel);
|
||||
int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll);
|
||||
int mt8195_afe_get_default_mclk_source_by_rate(int rate);
|
||||
int mt8195_afe_init_clock(struct mtk_base_afe *afe);
|
||||
void mt8195_afe_deinit_clock(struct mtk_base_afe *afe);
|
||||
int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
|
||||
void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
|
||||
int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk);
|
||||
void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk);
|
||||
int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk);
|
||||
void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk);
|
||||
int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
|
||||
unsigned int rate);
|
||||
int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
|
||||
struct clk *parent);
|
||||
int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe);
|
||||
int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe);
|
||||
int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe);
|
||||
int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe);
|
||||
|
||||
#endif
|
||||
158
sound/soc/mediatek/mt8195/mt8195-afe-common.h
Normal file
158
sound/soc/mediatek/mt8195/mt8195-afe-common.h
Normal file
@ -0,0 +1,158 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* mt8195-afe-common.h -- Mediatek 8195 audio driver definitions
|
||||
*
|
||||
* Copyright (c) 2021 MediaTek Inc.
|
||||
* Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
|
||||
* Trevor Wu <trevor.wu@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef _MT_8195_AFE_COMMON_H_
|
||||
#define _MT_8195_AFE_COMMON_H_
|
||||
|
||||
#include <sound/soc.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/regmap.h>
|
||||
#include "../common/mtk-base-afe.h"
|
||||
|
||||
enum {
|
||||
MT8195_DAI_START,
|
||||
MT8195_AFE_MEMIF_START = MT8195_DAI_START,
|
||||
MT8195_AFE_MEMIF_DL2 = MT8195_AFE_MEMIF_START,
|
||||
MT8195_AFE_MEMIF_DL3,
|
||||
MT8195_AFE_MEMIF_DL6,
|
||||
MT8195_AFE_MEMIF_DL7,
|
||||
MT8195_AFE_MEMIF_DL8,
|
||||
MT8195_AFE_MEMIF_DL10,
|
||||
MT8195_AFE_MEMIF_DL11,
|
||||
MT8195_AFE_MEMIF_UL_START,
|
||||
MT8195_AFE_MEMIF_UL1 = MT8195_AFE_MEMIF_UL_START,
|
||||
MT8195_AFE_MEMIF_UL2,
|
||||
MT8195_AFE_MEMIF_UL3,
|
||||
MT8195_AFE_MEMIF_UL4,
|
||||
MT8195_AFE_MEMIF_UL5,
|
||||
MT8195_AFE_MEMIF_UL6,
|
||||
MT8195_AFE_MEMIF_UL8,
|
||||
MT8195_AFE_MEMIF_UL9,
|
||||
MT8195_AFE_MEMIF_UL10,
|
||||
MT8195_AFE_MEMIF_END,
|
||||
MT8195_AFE_MEMIF_NUM = (MT8195_AFE_MEMIF_END - MT8195_AFE_MEMIF_START),
|
||||
MT8195_AFE_IO_START = MT8195_AFE_MEMIF_END,
|
||||
MT8195_AFE_IO_DL_SRC = MT8195_AFE_IO_START,
|
||||
MT8195_AFE_IO_DPTX,
|
||||
MT8195_AFE_IO_ETDM_START,
|
||||
MT8195_AFE_IO_ETDM1_IN = MT8195_AFE_IO_ETDM_START,
|
||||
MT8195_AFE_IO_ETDM2_IN,
|
||||
MT8195_AFE_IO_ETDM1_OUT,
|
||||
MT8195_AFE_IO_ETDM2_OUT,
|
||||
MT8195_AFE_IO_ETDM3_OUT,
|
||||
MT8195_AFE_IO_ETDM_END,
|
||||
MT8195_AFE_IO_ETDM_NUM =
|
||||
(MT8195_AFE_IO_ETDM_END - MT8195_AFE_IO_ETDM_START),
|
||||
MT8195_AFE_IO_PCM = MT8195_AFE_IO_ETDM_END,
|
||||
MT8195_AFE_IO_UL_SRC1,
|
||||
MT8195_AFE_IO_UL_SRC2,
|
||||
MT8195_AFE_IO_END,
|
||||
MT8195_AFE_IO_NUM = (MT8195_AFE_IO_END - MT8195_AFE_IO_START),
|
||||
MT8195_DAI_END = MT8195_AFE_IO_END,
|
||||
MT8195_DAI_NUM = (MT8195_DAI_END - MT8195_DAI_START),
|
||||
};
|
||||
|
||||
enum {
|
||||
MT8195_TOP_CG_A1SYS_TIMING,
|
||||
MT8195_TOP_CG_A2SYS_TIMING,
|
||||
MT8195_TOP_CG_26M_TIMING,
|
||||
MT8195_TOP_CG_NUM,
|
||||
};
|
||||
|
||||
enum {
|
||||
MT8195_AFE_IRQ_1,
|
||||
MT8195_AFE_IRQ_2,
|
||||
MT8195_AFE_IRQ_3,
|
||||
MT8195_AFE_IRQ_8,
|
||||
MT8195_AFE_IRQ_9,
|
||||
MT8195_AFE_IRQ_10,
|
||||
MT8195_AFE_IRQ_13,
|
||||
MT8195_AFE_IRQ_14,
|
||||
MT8195_AFE_IRQ_15,
|
||||
MT8195_AFE_IRQ_16,
|
||||
MT8195_AFE_IRQ_17,
|
||||
MT8195_AFE_IRQ_18,
|
||||
MT8195_AFE_IRQ_19,
|
||||
MT8195_AFE_IRQ_20,
|
||||
MT8195_AFE_IRQ_21,
|
||||
MT8195_AFE_IRQ_22,
|
||||
MT8195_AFE_IRQ_23,
|
||||
MT8195_AFE_IRQ_24,
|
||||
MT8195_AFE_IRQ_25,
|
||||
MT8195_AFE_IRQ_26,
|
||||
MT8195_AFE_IRQ_27,
|
||||
MT8195_AFE_IRQ_28,
|
||||
MT8195_AFE_IRQ_NUM,
|
||||
};
|
||||
|
||||
enum {
|
||||
MT8195_ETDM_OUT1_1X_EN = 9,
|
||||
MT8195_ETDM_OUT2_1X_EN = 10,
|
||||
MT8195_ETDM_OUT3_1X_EN = 11,
|
||||
MT8195_ETDM_IN1_1X_EN = 12,
|
||||
MT8195_ETDM_IN2_1X_EN = 13,
|
||||
MT8195_ETDM_IN1_NX_EN = 25,
|
||||
MT8195_ETDM_IN2_NX_EN = 26,
|
||||
};
|
||||
|
||||
enum {
|
||||
MT8195_MTKAIF_MISO_0,
|
||||
MT8195_MTKAIF_MISO_1,
|
||||
MT8195_MTKAIF_MISO_2,
|
||||
MT8195_MTKAIF_MISO_NUM,
|
||||
};
|
||||
|
||||
struct mtk_dai_memif_irq_priv {
|
||||
unsigned int asys_timing_sel;
|
||||
};
|
||||
|
||||
struct mtkaif_param {
|
||||
bool mtkaif_calibration_ok;
|
||||
int mtkaif_chosen_phase[MT8195_MTKAIF_MISO_NUM];
|
||||
int mtkaif_phase_cycle[MT8195_MTKAIF_MISO_NUM];
|
||||
int mtkaif_dmic_on;
|
||||
int mtkaif_adda6_only;
|
||||
};
|
||||
|
||||
struct clk;
|
||||
|
||||
struct mt8195_afe_private {
|
||||
struct clk **clk;
|
||||
struct clk_lookup **lookup;
|
||||
struct regmap *topckgen;
|
||||
int pm_runtime_bypass_reg_ctl;
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
struct dentry **debugfs_dentry;
|
||||
#endif
|
||||
int afe_on_ref_cnt;
|
||||
int top_cg_ref_cnt[MT8195_TOP_CG_NUM];
|
||||
spinlock_t afe_ctrl_lock; /* Lock for afe control */
|
||||
struct mtk_dai_memif_irq_priv irq_priv[MT8195_AFE_IRQ_NUM];
|
||||
struct mtkaif_param mtkaif_params;
|
||||
|
||||
/* dai */
|
||||
void *dai_priv[MT8195_DAI_NUM];
|
||||
};
|
||||
|
||||
int mt8195_afe_fs_timing(unsigned int rate);
|
||||
/* dai register */
|
||||
int mt8195_dai_adda_register(struct mtk_base_afe *afe);
|
||||
int mt8195_dai_etdm_register(struct mtk_base_afe *afe);
|
||||
int mt8195_dai_pcm_register(struct mtk_base_afe *afe);
|
||||
|
||||
#define MT8195_SOC_ENUM_EXT(xname, xenum, xhandler_get, xhandler_put, id) \
|
||||
{ \
|
||||
.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
|
||||
.info = snd_soc_info_enum_double, \
|
||||
.get = xhandler_get, .put = xhandler_put, \
|
||||
.device = id, \
|
||||
.private_value = (unsigned long)&xenum, \
|
||||
}
|
||||
|
||||
#endif
|
||||
3281
sound/soc/mediatek/mt8195/mt8195-afe-pcm.c
Normal file
3281
sound/soc/mediatek/mt8195/mt8195-afe-pcm.c
Normal file
File diff suppressed because it is too large
Load Diff
2796
sound/soc/mediatek/mt8195/mt8195-reg.h
Normal file
2796
sound/soc/mediatek/mt8195/mt8195-reg.h
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user