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mfd: cros_ec: Add SCP Core-1 as a new CrOS EC MCU
MT8195 System Companion Processors(SCP) is a dual-core RISC-V MCU. Add a new CrOS feature ID to represent the SCP's 2nd core. The 1st core is referred to as 'core 0', and the 2nd core is referred to as 'core 1'. Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20220601112201.15510-16-tinghan.shen@mediatek.com
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@ -64,6 +64,11 @@ static const struct cros_feature_to_name cros_mcu_devices[] = {
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.name = CROS_EC_DEV_SCP_NAME,
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.desc = "System Control Processor",
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},
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{
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.id = EC_FEATURE_SCP_C1,
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.name = CROS_EC_DEV_SCP_C1_NAME,
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.desc = "System Control Processor 2nd Core",
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},
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{
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.id = EC_FEATURE_TOUCHPAD,
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.name = CROS_EC_DEV_TP_NAME,
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@ -1300,6 +1300,8 @@ enum ec_feature_code {
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* mux.
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*/
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EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43,
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/* The MCU is a System Companion Processor (SCP) 2nd Core. */
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EC_FEATURE_SCP_C1 = 45,
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};
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#define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32)
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@ -19,6 +19,7 @@
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#define CROS_EC_DEV_ISH_NAME "cros_ish"
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#define CROS_EC_DEV_PD_NAME "cros_pd"
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#define CROS_EC_DEV_SCP_NAME "cros_scp"
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#define CROS_EC_DEV_SCP_C1_NAME "cros_scp_c1"
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#define CROS_EC_DEV_TP_NAME "cros_tp"
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/*
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