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arm64: Add sysreg header generation scripting
The arm64 kernel requires some metadata for each system register it may need to access. Currently we have: * A SYS_<regname> definition which sorresponds to a sys_reg() macro. This is used both to look up a sysreg by encoding (e.g. in KVM), and also to generate code to access a sysreg where the assembler is unaware of the specific sysreg encoding. Where assemblers support the S3_<op1>_C<crn>_C<crm>_<op2> syntax for system registers, we could use this rather than manually assembling the instructions. However, we don't have consistent definitions for these and we currently still need to handle toolchains that lack this feature. * A set of <regname>_<fieldname>_SHIFT and <regname>_<fieldname>_MASK definitions, which can be used to extract fields from the register, or to construct a register from a set of fields. These do not follow the convention used by <linux/bitfield.h>, and the masks are not shifted into place, preventing their use in FIELD_PREP() and FIELD_GET(). We require the SHIFT definitions for inline assembly (and WIDTH definitions would be helpful for UBFX/SBFX), so we cannot only define a shifted MASK. Defining a SHIFT, WIDTH, shifted MASK and unshifted MASK is tedious and error-prone and life is much easier when they can be relied up to exist when writing code. * A set of <regname>_<fieldname>_<valname> definitions for each enumerated value a field may hold. These are used when identifying the presence of features. Atop of this, other code has to build up metadata at runtime (e.g. the sets of RES0/RES1 bits in a register). This patch adds scripting so that we can have an easier-to-manage canonical representation of this metadata, from which we can generate all the definitions necessary for various use-cases, e.g. | #define REG_ID_AA64ISAR0_EL1 S3_0_C0_C6_0 | #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) | #define SYS_ID_AA64ISAR0_EL1_Op0 3 | #define SYS_ID_AA64ISAR0_EL1_Op1 0 | #define SYS_ID_AA64ISAR0_EL1_CRn 0 | #define SYS_ID_AA64ISAR0_EL1_CRm 6 | #define SYS_ID_AA64ISAR0_EL1_Op2 0 | #define ID_AA64ISAR0_EL1_RNDR GENMASK(63, 60) | #define ID_AA64ISAR0_EL1_RNDR_MASK GENMASK(63, 60) | #define ID_AA64ISAR0_EL1_RNDR_SHIFT 60 | #define ID_AA64ISAR0_EL1_RNDR_WIDTH 4 | #define ID_AA64ISAR0_EL1_RNDR_NI UL(0b0000) | #define ID_AA64ISAR0_EL1_RNDR_IMP UL(0b0001) The script requires that all bits in the register be specified and that there be no overlapping fields. This helps the script spot errors in the input but means that the few registers which change layout at runtime depending on things like virtualisation settings will need some manual handling. No actual register conversions are done here but a header for the register data with some documention of the format is provided. For cases where multiple registers share a layout (eg, when identical controls are provided at multiple ELs) the register fields can be defined once and referenced from the actual registers, currently we do not generate actual defines for the individual registers. At the moment this is only intended to express metadata from the architecture, and does not handle policy imposed by the kernel, such as values exposed to userspace or VMs. In future this could be extended to express such information. This script was mostly written by Mark Rutland but has been extended by Mark Brown to improve validation of input and better integrate with the kernel. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Co-Developed-by: Mark Brown <broonie@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220503170233.507788-9-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Mark Rutland
Catalin Marinas
parent
0eda2ec489
commit
66847e0618
261
arch/arm64/tools/gen-sysreg.awk
Executable file
261
arch/arm64/tools/gen-sysreg.awk
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#!/bin/awk -f
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# SPDX-License-Identifier: GPL-2.0
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# gen-sysreg.awk: arm64 sysreg header generator
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#
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# Usage: awk -f gen-sysreg.awk sysregs.txt
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# Log an error and terminate
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function fatal(msg) {
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print "Error at " NR ": " msg > "/dev/stderr"
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exit 1
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}
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# Sanity check that the start or end of a block makes sense at this point in
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# the file. If not, produce an error and terminate.
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#
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# @this - the $Block or $EndBlock
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# @prev - the only valid block to already be in (value of @block)
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# @new - the new value of @block
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function change_block(this, prev, new) {
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if (block != prev)
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fatal("unexpected " this " (inside " block ")")
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block = new
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}
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# Sanity check the number of records for a field makes sense. If not, produce
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# an error and terminate.
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function expect_fields(nf) {
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if (NF != nf)
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fatal(NF " fields found where " nf " expected")
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}
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# Print a CPP macro definition, padded with spaces so that the macro bodies
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# line up in a column
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function define(name, val) {
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printf "%-48s%s\n", "#define " name, val
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}
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# Print standard BITMASK/SHIFT/WIDTH CPP definitions for a field
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function define_field(reg, field, msb, lsb) {
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define(reg "_" field, "GENMASK(" msb ", " lsb ")")
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define(reg "_" field "_MASK", "GENMASK(" msb ", " lsb ")")
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define(reg "_" field "_SHIFT", lsb)
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define(reg "_" field "_WIDTH", msb - lsb + 1)
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}
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# Parse a "<msb>[:<lsb>]" string into the global variables @msb and @lsb
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function parse_bitdef(reg, field, bitdef, _bits)
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{
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if (bitdef ~ /^[0-9]+$/) {
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msb = bitdef
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lsb = bitdef
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} else if (split(bitdef, _bits, ":") == 2) {
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msb = _bits[1]
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lsb = _bits[2]
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} else {
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fatal("invalid bit-range definition '" bitdef "'")
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}
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if (msb != next_bit)
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fatal(reg "." field " starts at " msb " not " next_bit)
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if (63 < msb || msb < 0)
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fatal(reg "." field " invalid high bit in '" bitdef "'")
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if (63 < lsb || lsb < 0)
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fatal(reg "." field " invalid low bit in '" bitdef "'")
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if (msb < lsb)
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fatal(reg "." field " invalid bit-range '" bitdef "'")
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if (low > high)
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fatal(reg "." field " has invalid range " high "-" low)
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next_bit = lsb - 1
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}
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BEGIN {
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print "#ifndef __ASM_SYSREG_DEFS_H"
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print "#define __ASM_SYSREG_DEFS_H"
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print ""
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print "/* Generated file - do not edit */"
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block = "None"
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}
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END {
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print "#endif /* __ASM_SYSREG_DEFS_H */"
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}
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# skip blank lines and comment lines
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/^$/ { next }
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/^#/ { next }
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/^SysregFields/ {
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change_block("SysregFields", "None", "SysregFields")
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expect_fields(2)
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reg = $2
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res0 = "UL(0)"
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res1 = "UL(0)"
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print ""
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next_bit = 63
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next
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}
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/^EndSysregFields/ {
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if (next_bit > 0)
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fatal("Unspecified bits in " reg)
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change_block("EndSysregFields", "SysregFields", "None")
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define(reg "_RES0", "(" res0 ")")
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define(reg "_RES1", "(" res1 ")")
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print ""
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reg = null
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res0 = null
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res1 = null
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next
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}
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/^Sysreg/ {
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change_block("Sysreg", "None", "Sysreg")
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expect_fields(7)
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reg = $2
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op0 = $3
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op1 = $4
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crn = $5
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crm = $6
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op2 = $7
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res0 = "UL(0)"
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res1 = "UL(0)"
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define("REG_" reg, "S" op0 "_" op1 "_C" crn "_C" crm "_" op2)
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define("SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " op2 ")")
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define("SYS_" reg "_Op0", op0)
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define("SYS_" reg "_Op1", op1)
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define("SYS_" reg "_CRn", crn)
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define("SYS_" reg "_CRm", crm)
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define("SYS_" reg "_Op2", op2)
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print ""
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next_bit = 63
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next
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}
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/^EndSysreg/ {
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if (next_bit > 0)
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fatal("Unspecified bits in " reg)
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change_block("EndSysreg", "Sysreg", "None")
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if (res0 != null)
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define(reg "_RES0", "(" res0 ")")
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if (res1 != null)
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define(reg "_RES1", "(" res1 ")")
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print ""
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reg = null
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op0 = null
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op1 = null
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crn = null
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crm = null
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op2 = null
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res0 = null
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res1 = null
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next
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}
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# Currently this is effectivey a comment, in future we may want to emit
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# defines for the fields.
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/^Fields/ && (block == "Sysreg") {
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expect_fields(2)
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if (next_bit != 63)
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fatal("Some fields already defined for " reg)
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print "/* See " $2 " */"
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print ""
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next_bit = 0
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res0 = null
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res1 = null
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next
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}
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/^Res0/ && (block == "Sysreg" || block == "SysregFields") {
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expect_fields(2)
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parse_bitdef(reg, "RES0", $2)
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field = "RES0_" msb "_" lsb
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res0 = res0 " | GENMASK_ULL(" msb ", " lsb ")"
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next
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}
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/^Res1/ && (block == "Sysreg" || block == "SysregFields") {
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expect_fields(2)
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parse_bitdef(reg, "RES1", $2)
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field = "RES1_" msb "_" lsb
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res1 = res1 " | GENMASK_ULL(" msb ", " lsb ")"
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next
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}
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/^Field/ && (block == "Sysreg" || block == "SysregFields") {
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expect_fields(3)
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field = $3
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parse_bitdef(reg, field, $2)
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define_field(reg, field, msb, lsb)
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print ""
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next
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}
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/^Enum/ {
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change_block("Enum", "Sysreg", "Enum")
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expect_fields(3)
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field = $3
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parse_bitdef(reg, field, $2)
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define_field(reg, field, msb, lsb)
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next
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}
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/^EndEnum/ {
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change_block("EndEnum", "Enum", "Sysreg")
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field = null
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msb = null
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lsb = null
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print ""
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next
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}
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/0b[01]+/ && block = "Enum" {
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expect_fields(2)
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val = $1
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name = $2
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define(reg "_" field "_" name, "UL(" val ")")
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next
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}
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# Any lines not handled by previous rules are unexpected
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{
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fatal("unhandled statement")
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}
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48
arch/arm64/tools/sysreg
Normal file
48
arch/arm64/tools/sysreg
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@ -0,0 +1,48 @@
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# SPDX-License-Identifier: GPL-2.0-only
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#
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# System register metadata
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# Each System register is described by a Sysreg block:
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# Sysreg <name> <op0> <op1> <crn> <crm> <op2>
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# <field>
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# ...
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# EndSysreg
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# Within a Sysreg block, each field can be described as one of:
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# Res0 <msb>[:<lsb>]
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# Res1 <msb>[:<lsb>]
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# Field <msb>[:<lsb>] <name>
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# Enum <msb>[:<lsb>] <name>
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# <enumval> <enumname>
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# ...
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# EndEnum
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# Alternatively if multiple registers share the same layout then
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# a SysregFields block can be used to describe the shared layout
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# SysregFields <fieldsname>
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# <field>
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# ...
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# EndSysregFields
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# and referenced from within the Sysreg:
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# Sysreg <name> <op0> <op1> <crn> <crm> <op2>
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# Fields <fieldsname>
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# EndSysreg
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# For ID registers we adopt a few conventions for translating the
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# language in the ARM into defines:
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#
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# NI - Not implemented
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# IMP - Implemented
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#
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# In general it is recommended that new enumeration items be named for the
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# feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration
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# item ACCDATA) though it may be more taseful to do something else.
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