Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-12-24 20:01:55 +00:00
Code Issues Packages Projects Releases Wiki Activity

clk: qcom: gcc: fix sm8150 GPU and NPU clocks

Browse Source 
Fix the parents and set BRANCH_HALT_SKIP. From the downstream driver it
should be a 500us delay and not skip, however this matches what was done
for other clocks that had 500us delay in downstream.

Fixes: f73a4230d5 ("clk: qcom: gcc: Add GPU and NPU clocks for SM8150")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200709135251.643-2-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Jonathan Marek 2020-07-09 09:52:32 -04:00 committed by Stephen Boyd
parent ba937f5109
commit 667f39b59b
1 changed files with 6 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/clk/qcom/gcc-sm8150.c
View File

@ -1617,6 +1617,7 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = {
}; };
static struct clk_branch gcc_gpu_gpll0_clk_src = { static struct clk_branch gcc_gpu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = { .clkr = {
.enable_reg = 0x52004, .enable_reg = 0x52004,
.enable_mask = BIT(15), .enable_mask = BIT(15),
@ -1632,13 +1633,14 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = {
}; };
static struct clk_branch gcc_gpu_gpll0_div_clk_src = { static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = { .clkr = {
.enable_reg = 0x52004, .enable_reg = 0x52004,
.enable_mask = BIT(16), .enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src", .name = "gcc_gpu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw *[]){ .parent_hws = (const struct clk_hw *[]){
&gcc_gpu_gpll0_clk_src.clkr.hw }, &gpll0_out_even.clkr.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops, .ops = &clk_branch2_ops,
@ -1729,6 +1731,7 @@ static struct clk_branch gcc_npu_cfg_ahb_clk = {
}; };
static struct clk_branch gcc_npu_gpll0_clk_src = { static struct clk_branch gcc_npu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = { .clkr = {
.enable_reg = 0x52004, .enable_reg = 0x52004,
.enable_mask = BIT(18), .enable_mask = BIT(18),
@ -1744,13 +1747,14 @@ static struct clk_branch gcc_npu_gpll0_clk_src = {
}; };
static struct clk_branch gcc_npu_gpll0_div_clk_src = { static struct clk_branch gcc_npu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = { .clkr = {
.enable_reg = 0x52004, .enable_reg = 0x52004,
.enable_mask = BIT(19), .enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_npu_gpll0_div_clk_src", .name = "gcc_npu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw *[]){ .parent_hws = (const struct clk_hw *[]){
&gcc_npu_gpll0_clk_src.clkr.hw }, &gpll0_out_even.clkr.hw },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops, .ops = &clk_branch2_ops,