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drm/i915/selftests: Set always_coherent to false when reading from CPU

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Commit 8d4ba9fc1c ("drm/i915/selftests: Pick correct caching mode.")
was not complete  as for non LLC  sharing platforms cpu read can happen
from LLC which probably doesn't have the latest changes made by GPU.

Cc: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>
Fixes: 8d4ba9fc1c ("drm/i915/selftests: Pick correct caching mode.")
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240516151403.2875-1-nirmoy.das@intel.com
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
(cherry picked from commit 007ed70831)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Nirmoy Das 2024-05-16 17:14:03 +02:00 committed by Jani Nikula
parent d4f36db623
commit 659a3062c7
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
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@ -196,7 +196,7 @@ static int verify_access(struct drm_i915_private *i915,
if (err)
goto out_file;
mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, true);
mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, false);
vaddr = i915_gem_object_pin_map_unlocked(native_obj, mode);
if (IS_ERR(vaddr)) {
err = PTR_ERR(vaddr);