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Qualcomm ARM64 DeviceTree updates for v6.6

Browse Source 
Initial support for the SM4450 platform and the QRD device thereon is
 added.
 
 The IPQ5018 platform is introduced, and the RDP432-C2 board thereon.
 
 A shared definition of the IPQ5332 RDP is introduced, as is GPIO-based
 LEDs and buttons.
 
 On the IPQ9574 RDP433 USB, CPU cooling maps and regulators are added.
 
 On MSM8916, the D3 camera mezzanine is improved and refactored out to
 its own dts. The Samsung Galaxy S4 Mini gains support for its PMIC with
 charger, while Samsung Galaxy J5 and E5 gains touchscreen support.
 
 A few fixes for MSM8939 are introduced, and initial support for Samsung
 Galaxy A7 is add.
 
 Support for scaling the cache bus fabric is introduced on MSM8996. A
 missing interrupt for the USB2 controller is added. The touchscreen vio
 supply on Xiaomi Mi 5 is corrected, and a few other cleanups are
 introduces across other devices.
 
 The display controller is introduced for MSM8998, a few clock fixes are
 introduced and missing power domains are added for the multimedia
 subsystem iommu.
 
 Reserved memory-regions and reserved GPIO lists are updated for the
 QDU/QRU1000 IDPs.
 
 USB3 PHY is added to the QCM2290, the RB1 gains regulators and GPU is
 enabled for the RB2.
 
 PCIe and Ethernet support is introduced on SA8775P, and enabled for the
 Ride board.
 
 On SC7180 the PSCI integration is refactored, to allow supporting
 devices with the Qualcomm firmware. BWMON is introduced, alongside the
 CPUfreq-based bus voting.
 
 A number of fixes are added for SC8180X, on the Primus and Lenovo Flex
 5G devices pmic_glink is introduced and wired up, to provide support for
 external display.
 
 Missing SCM interconnect is added to SC8280XP, and the PDC is marked as
 wakeup-parent of TLMM. On the CRD the gpio for vreg_misc_3p3 is
 corrected and a few regulators are renamed to align with schematics. The
 Lenovo Thinkpad X13s gains camera activity LED and a set of previously
 reserved GPIOs are released. The SA8540P Ride platform gains RTC
 support.
 
 For SDM670 CPU and L3 frequency scaling is added, the PDC is introduced
 and wired up as wakeup-parent of the TLMM.
 
 On SDM845 the UFS controller gains interconnect path description,
 power-domain information is added to GCC and minimum frequency of the
 UFS ICE is corrected. On RB3 continuous splash memory region is
 described, and the camera subsystem is enabled. On the Lenovo Yoga C630
 a missing power supply for the display panel is added, and the debug
 UART is introduced.
 
 SDX75 RPMh power-domains and SPMI controller are introduces, the PMX75
 PMIC is described and added to the IDP.
 
 GPU description is added to SM6115, and together with display enabled on
 the Lenovo Tab P11.
 
 On SM635 BWMON is introduced for LLCC and DDR scaling. Display and GPU
 is added, and the PDC is registered as wakeup-parent of TLMM.
 
 L3 cache scaling is introduced on SM6375.
 
 The DSI PHY compatible and an interrupt for I2C7 are corrected for
 SM8150, on the Sony Xperia 1 and 5 the ramoops pmsg size is corrected.
 
 On SM8250 BWMONs are introduced for DDR and LLCC scaling, the UFS node
 gains interconnect paths, SMMU is marked as DMA coherent and dynamic
 power coefficients are updated. On Sony Xperia 1 II and 5 II GPIO line
 names are updated.
 
 On SM8350 missing cluster sleep states and LMH interrupts are added,
 the CPU compatibles are corrected and APR and LPASS pinctrl support is
 introduced. The HDK gains uSD card support and PMK8350 is added.
 
 For SM8450 support for RNG and RPMh stats are added, the ICE handling is
 extracted from the UFS node and the display subsystem gains a missing
 interconnect path. Thermal description is improved for the HDK.
 
 On SM8550 MTP and QRD the pmic_glink is introduced, to provide
 DisplayPort output. A missing regulator supply is also added.
 
 A few platforms that happens to share the RPMH power-domain resource
 identifier constants are migrated to new generic defines. ADC channel
 names are generalized on various PMICs.
 
 A variety of devices gain chassis-type, and the GIC_SPI constant is
 replacing the 0 across a few different platforms.
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Merge tag 'qcom-arm64-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

Qualcomm ARM64 DeviceTree updates for v6.6

Initial support for the SM4450 platform and the QRD device thereon is
added.

The IPQ5018 platform is introduced, and the RDP432-C2 board thereon.

A shared definition of the IPQ5332 RDP is introduced, as is GPIO-based
LEDs and buttons.

On the IPQ9574 RDP433 USB, CPU cooling maps and regulators are added.

On MSM8916, the D3 camera mezzanine is improved and refactored out to
its own dts. The Samsung Galaxy S4 Mini gains support for its PMIC with
charger, while Samsung Galaxy J5 and E5 gains touchscreen support.

A few fixes for MSM8939 are introduced, and initial support for Samsung
Galaxy A7 is add.

Support for scaling the cache bus fabric is introduced on MSM8996. A
missing interrupt for the USB2 controller is added. The touchscreen vio
supply on Xiaomi Mi 5 is corrected, and a few other cleanups are
introduces across other devices.

The display controller is introduced for MSM8998, a few clock fixes are
introduced and missing power domains are added for the multimedia
subsystem iommu.

Reserved memory-regions and reserved GPIO lists are updated for the
QDU/QRU1000 IDPs.

USB3 PHY is added to the QCM2290, the RB1 gains regulators and GPU is
enabled for the RB2.

PCIe and Ethernet support is introduced on SA8775P, and enabled for the
Ride board.

On SC7180 the PSCI integration is refactored, to allow supporting
devices with the Qualcomm firmware. BWMON is introduced, alongside the
CPUfreq-based bus voting.

A number of fixes are added for SC8180X, on the Primus and Lenovo Flex
5G devices pmic_glink is introduced and wired up, to provide support for
external display.

Missing SCM interconnect is added to SC8280XP, and the PDC is marked as
wakeup-parent of TLMM. On the CRD the gpio for vreg_misc_3p3 is
corrected and a few regulators are renamed to align with schematics. The
Lenovo Thinkpad X13s gains camera activity LED and a set of previously
reserved GPIOs are released. The SA8540P Ride platform gains RTC
support.

For SDM670 CPU and L3 frequency scaling is added, the PDC is introduced
and wired up as wakeup-parent of the TLMM.

On SDM845 the UFS controller gains interconnect path description,
power-domain information is added to GCC and minimum frequency of the
UFS ICE is corrected. On RB3 continuous splash memory region is
described, and the camera subsystem is enabled. On the Lenovo Yoga C630
a missing power supply for the display panel is added, and the debug
UART is introduced.

SDX75 RPMh power-domains and SPMI controller are introduces, the PMX75
PMIC is described and added to the IDP.

GPU description is added to SM6115, and together with display enabled on
the Lenovo Tab P11.

On SM635 BWMON is introduced for LLCC and DDR scaling. Display and GPU
is added, and the PDC is registered as wakeup-parent of TLMM.

L3 cache scaling is introduced on SM6375.

The DSI PHY compatible and an interrupt for I2C7 are corrected for
SM8150, on the Sony Xperia 1 and 5 the ramoops pmsg size is corrected.

On SM8250 BWMONs are introduced for DDR and LLCC scaling, the UFS node
gains interconnect paths, SMMU is marked as DMA coherent and dynamic
power coefficients are updated. On Sony Xperia 1 II and 5 II GPIO line
names are updated.

On SM8350 missing cluster sleep states and LMH interrupts are added,
the CPU compatibles are corrected and APR and LPASS pinctrl support is
introduced. The HDK gains uSD card support and PMK8350 is added.

For SM8450 support for RNG and RPMh stats are added, the ICE handling is
extracted from the UFS node and the display subsystem gains a missing
interconnect path. Thermal description is improved for the HDK.

On SM8550 MTP and QRD the pmic_glink is introduced, to provide
DisplayPort output. A missing regulator supply is also added.

A few platforms that happens to share the RPMH power-domain resource
identifier constants are migrated to new generic defines. ADC channel
names are generalized on various PMICs.

A variety of devices gain chassis-type, and the GIC_SPI constant is
replacing the 0 across a few different platforms.

* tag 'qcom-arm64-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (215 commits)
  arm64: dts: qcom: sdm845-db845c: Mark cont splash memory region as reserved
  arm64: dts: qcom: sm6350: Hook up PDC as wakeup-parent of TLMM
  arm64: dts: qcom: sdm670: Hook up PDC as wakeup-parent of TLMM
  arm64: dts: qcom: sa8775p: Hook up PDC as wakeup-parent of TLMM
  arm64: dts: qcom: sc8280xp: Hook up PDC as wakeup-parent of TLMM
  arm64: dts: qcom: sdm670: Add PDC
  arm64: dts: qcom: msm8916-samsung-e5: Add touchscreen
  arm64: dts: qcom: sc7180: Split up TF-A related PSCI configuration
  arm64: dts: qcom: sc8280xp-x13s: Add camera activity LED
  arm64: dts: qcom: sc8280xp-x13s: Unreserve NC pins
  arm64: dts: qcom: msm8998: Add DPU1 nodes
  arm64: dts: qcom: msm8996: Fix dsi1 interrupts
  arm64: dts: qcom: sdx75-idp: Add regulator nodes
  arm64: dts: qcom: sdx75: Add rpmhpd node
  arm64: dts: qcom: sdx75-idp: Add pmics supported in SDX75
  arm64: dts: qcom: Add pmx75 PMIC dtsi
  arm64: dts: qcom: Add pm7550ba PMIC dtsi
  arm64: dts: qcom: Add pinctrl gpio support for pm7250b
  arm64: dts: qcom: sdx75: Add spmi node
  arm64: dts: qcom: msm8998: Add missing power domain to MMSS SMMU
  ...

Link: https://lore.kernel.org/r/20230819034551.2537866-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-08-21 21:37:53 -04:00
commit 6522fbd48a
174 changed files with 8956 additions and 1972 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/arm/qcom-soc.yaml
View File

@ -31,7 +31,7 @@ properties:
compatible:
oneOf:
# Preferred naming style for compatibles of SoC components:
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+-.*$"
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+(pro)?-.*$"
- pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
# Legacy namings - variations of existing patterns/compatibles are OK,

14
Documentation/devicetree/bindings/arm/qcom.yaml
View File

@ -30,6 +30,7 @@ description: |
apq8084
apq8096
ipq4018
ipq5018
ipq5332
ipq6018
ipq8074
@ -72,6 +73,7 @@ description: |
sdx65
sdx75
sm4250
sm4450
sm6115
sm6115p
sm6125
@ -104,6 +106,7 @@ description: |
hk10-c2
idp
liquid
rdp432-c2
mtp
qrd
rb2
@ -186,6 +189,7 @@ properties:
- items:
- enum:
- samsung,a7
- sony,kanuti-tulip
- square,apq8039-t2
- const: qcom,msm8939
@ -339,6 +343,11 @@ properties:
- qcom,ipq4019-dk04.1-c1
- const: qcom,ipq4019
- items:
- enum:
- qcom,ipq5018-rdp432-c2
- const: qcom,ipq5018
- items:
- enum:
- qcom,ipq5332-ap-mi01.2
@ -902,6 +911,11 @@ properties:
- const: qcom,qrb4210
- const: qcom,sm4250
- items:
- enum:
- qcom,sm4450-qrd
- const: qcom,sm4450
- items:
- enum:
- fxtec,pro1x

63
Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml Normal file
View File

@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on IPQ5018
maintainers:
- Sricharan Ramabadhran <quic_srichara@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ5018
See also::
include/dt-bindings/clock/qcom,ipq5018-gcc.h
include/dt-bindings/reset/qcom,ipq5018-gcc.h
properties:
compatible:
const: qcom,gcc-ipq5018
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: PCIE20 PHY0 pipe clock source
- description: PCIE20 PHY1 pipe clock source
- description: USB3 PHY pipe clock source
- description: GEPHY RX clock source
- description: GEPHY TX clock source
- description: UNIPHY RX clock source
- description: UNIPHY TX clk source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
clock-controller@1800000 {
compatible = "qcom,gcc-ipq5018";
reg = <0x01800000 0x80000>;
clocks = <&xo_board_clk>,
<&sleep_clk>,
<&pcie20_phy0_pipe_clk>,
<&pcie20_phy1_pipe_clk>,
<&usb3_phy0_pipe_clk>,
<&gephy_rx_clk>,
<&gephy_tx_clk>,
<&uniphy_rx_clk>,
<&uniphy_tx_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

4
arch/arm64/boot/dts/qcom/Makefile
View File

@ -1,9 +1,11 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-d3-camera-mezzanine.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb
@ -39,6 +41,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-uf896.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-ufi001c.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8939-samsung-a7.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8939-sony-xperia-kanuti-tulip.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8953-motorola-potter.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-daisy.dtb
@ -186,6 +189,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdx75-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb

81
arch/arm64/boot/dts/qcom/apq8016-sbc-d3-camera-mezzanine.dts Normal file
View File

@ -0,0 +1,81 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Ltd.
*/
/dts-v1/;
#include "apq8016-sbc.dts"
/ {
camera_vdddo_1v8: camera-vdddo-1v8 {
compatible = "regulator-fixed";
regulator-name = "camera_vdddo";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
camera_vdda_2v8: camera-vdda-2v8 {
compatible = "regulator-fixed";
regulator-name = "camera_vdda";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
camera_vddd_1v5: camera-vddd-1v5 {
compatible = "regulator-fixed";
regulator-name = "camera_vddd";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
};
&camss {
status = "okay";
ports {
port@0 {
reg = <0>;
csiphy0_ep: endpoint {
data-lanes = <0 2>;
remote-endpoint = <&ov5640_ep>;
};
};
};
};
&cci {
status = "okay";
};
&cci_i2c0 {
camera_rear@3b {
compatible = "ovti,ov5640";
reg = <0x3b>;
powerdown-gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&camera_rear_default>;
clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
clock-names = "xclk";
assigned-clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
assigned-clock-rates = <23880000>;
DOVDD-supply = <&camera_vdddo_1v8>;
AVDD-supply = <&camera_vdda_2v8>;
DVDD-supply = <&camera_vddd_1v5>;
port {
ov5640_ep: endpoint {
data-lanes = <1 2>;
remote-endpoint = <&csiphy0_ep>;
};
};
};
};

85
arch/arm64/boot/dts/qcom/apq8016-sbc.dts
View File

@ -34,30 +34,6 @@
stdout-path = "serial0";
};
camera_vdddo_1v8: camera-vdddo-1v8 {
compatible = "regulator-fixed";
regulator-name = "camera_vdddo";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
camera_vdda_2v8: camera-vdda-2v8 {
compatible = "regulator-fixed";
regulator-name = "camera_vdda";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
camera_vddd_1v5: camera-vddd-1v5 {
compatible = "regulator-fixed";
regulator-name = "camera_vddd";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
reserved-memory {
ramoops@bff00000 {
compatible = "ramoops";
@ -77,7 +53,7 @@
usb_id: usb-id {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&tlmm 121 GPIO_ACTIVE_HIGH>;
id-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_id_default>;
};
@ -172,15 +148,13 @@
};
&blsp_i2c2 {
/* On Low speed expansion */
/* On Low speed expansion: LS-I2C0 */
status = "okay";
label = "LS-I2C0";
};
&blsp_i2c4 {
/* On High speed expansion */
/* On High speed expansion: HS-I2C2 */
status = "okay";
label = "HS-I2C2";
adv_bridge: bridge@39 {
status = "okay";
@ -228,21 +202,18 @@
};
&blsp_i2c6 {
/* On Low speed expansion */
/* On Low speed expansion: LS-I2C1 */
status = "okay";
label = "LS-I2C1";
};
&blsp_spi3 {
/* On High speed expansion */
/* On High speed expansion: HS-SPI1 */
status = "okay";
label = "HS-SPI1";
};
&blsp_spi5 {
/* On Low speed expansion */
/* On Low speed expansion: LS-SPI0 */
status = "okay";
label = "LS-SPI0";
};
&blsp_uart1 {
@ -257,50 +228,6 @@
&camss {
status = "okay";
ports {
port@0 {
reg = <0>;
csiphy0_ep: endpoint {
data-lanes = <0 2>;
remote-endpoint = <&ov5640_ep>;
status = "okay";
};
};
};
};
&cci {
status = "okay";
};
&cci_i2c0 {
camera_rear@3b {
compatible = "ovti,ov5640";
reg = <0x3b>;
enable-gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&camera_rear_default>;
clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
clock-names = "xclk";
clock-frequency = <23880000>;
vdddo-supply = <&camera_vdddo_1v8>;
vdda-supply = <&camera_vdda_2v8>;
vddd-supply = <&camera_vddd_1v5>;
/* No camera mezzanine by default */
status = "disabled";
port {
ov5640_ep: endpoint {
data-lanes = <0 2>;
remote-endpoint = <&csiphy0_ep>;
};
};
};
};
&lpass {

2
arch/arm64/boot/dts/qcom/apq8039-t2.dts
View File

@ -366,7 +366,6 @@
function = "gpio";
pins = "gpio107";
bias-pull-up;
input-enable;
};
};
@ -375,7 +374,6 @@
pinctrl-0 = <&pinctrl_otg_default>;
pinctrl-1 = <&pinctrl_otg_host>;
pinctrl-2 = <&pinctrl_otg_device>;
pin-switch-delay-us = <100000>;
usb-role-switch;
status = "okay";

27
arch/arm64/boot/dts/qcom/apq8096-db820c.dts
View File

@ -99,14 +99,14 @@
usb2_id: usb2-id {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>;
id-gpios = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb2_vbus_det_gpio>;
};
usb3_id: usb3-id {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>;
id-gpios = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb3_vbus_det_gpio>;
};
@ -138,8 +138,7 @@
};
&blsp1_i2c3 {
/* On Low speed expansion */
label = "LS-I2C0";
/* On Low speed expansion: LS-I2C0 */
status = "okay";
};
@ -168,14 +167,12 @@
};
&blsp2_i2c1 {
/* On High speed expansion */
label = "HS-I2C2";
/* On High speed expansion: HS-I2C2 */
status = "okay";
};
&blsp2_i2c1 {
/* On Low speed expansion */
label = "LS-I2C1";
/* On Low speed expansion: LS-I2C1 */
status = "okay";
};
@ -236,8 +233,8 @@
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mdss_hdmi_hpd_active &mdss_hdmi_ddc_active>;
pinctrl-1 = <&mdss_hdmi_hpd_suspend &mdss_hdmi_ddc_suspend>;
pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
core-vdda-supply = <&vreg_l12a_1p8>;
core-vcc-supply = <&vreg_s4a_1p8>;
@ -433,28 +430,28 @@
drive-strength = <2>;
};
mdss_hdmi_hpd_active: mdss_hdmi-hpd-active-state {
hdmi_hpd_active: hdmi-hpd-active-state {
pins = "gpio34";
function = "hdmi_hot";
bias-pull-down;
drive-strength = <16>;
};
mdss_hdmi_hpd_suspend: mdss_hdmi-hpd-suspend-state {
hdmi_hpd_suspend: hdmi-hpd-suspend-state {
pins = "gpio34";
function = "hdmi_hot";
bias-pull-down;
drive-strength = <2>;
};
mdss_hdmi_ddc_active: mdss_hdmi-ddc-active-state {
hdmi_ddc_active: hdmi-ddc-active-state {
pins = "gpio32", "gpio33";
function = "hdmi_ddc";
drive-strength = <2>;
bias-pull-up;
};
mdss_hdmi_ddc_suspend: mdss_hdmi-ddc-suspend-state {
hdmi_ddc_suspend: hdmi-ddc-suspend-state {
pins = "gpio32", "gpio33";
function = "hdmi_ddc";
drive-strength = <2>;
@ -1043,7 +1040,7 @@
};
};
mdss_hdmi-dai-link {
hdmi-dai-link {
link-name = "HDMI";
cpu {
sound-dai = <&q6afedai HDMI_RX>;

72
arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts Normal file
View File

@ -0,0 +1,72 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* IPQ5018 MP03.1-C2 board device tree source
*
* Copyright (c) 2023 The Linux Foundation. All rights reserved.
*/
/dts-v1/;
#include "ipq5018.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C2";
compatible = "qcom,ipq5018-rdp432-c2", "qcom,ipq5018";
aliases {
serial0 = &blsp1_uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&blsp1_uart1 {
pinctrl-0 = <&uart1_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhc_1 {
pinctrl-0 = <&sdc_default_state>;
pinctrl-names = "default";
mmc-ddr-1_8v;
mmc-hs200-1_8v;
max-frequency = <192000000>;
bus-width = <4>;
status = "okay";
};
&sleep_clk {
clock-frequency = <32000>;
};
&tlmm {
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio9";
function = "sdc1_clk";
drive-strength = <8>;
bias-disable;
};
cmd-pins {
pins = "gpio8";
function = "sdc1_cmd";
drive-strength = <8>;
bias-pull-up;
};
data-pins {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
function = "sdc1_data";
drive-strength = <8>;
bias-disable;
};
};
};
&xo_board_clk {
clock-frequency = <24000000>;
};

250
arch/arm64/boot/dts/qcom/ipq5018.dtsi Normal file
View File

@ -0,0 +1,250 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* IPQ5018 SoC device tree source
*
* Copyright (c) 2023 The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
clocks {
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
xo_board_clk: xo-board-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x80000>;
cache-unified;
};
};
firmware {
scm {
compatible = "qcom,scm-ipq5018", "qcom,scm";
};
};
memory@40000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0x0 0x40000000 0x0 0x0>;
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
tz_region: tz@4ac00000 {
reg = <0x0 0x4ac00000 0x0 0x200000>;
no-map;
};
};
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5018-tlmm";
reg = <0x01000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 47>;
interrupt-controller;
#interrupt-cells = <2>;
uart1_pins: uart1-state {
pins = "gpio31", "gpio32", "gpio33", "gpio34";
function = "blsp1_uart1";
drive-strength = <8>;
bias-pull-down;
};
};
gcc: clock-controller@1800000 {
compatible = "qcom,gcc-ipq5018";
reg = <0x01800000 0x80000>;
clocks = <&xo_board_clk>,
<&sleep_clk>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
sdhc_1: mmc@7804000 {
compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
reg = <0x7804000 0x1000>;
reg-names = "hc";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo_board_clk>;
clock-names = "iface", "core", "xo";
non-removable;
status = "disabled";
};
blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078af000 0x200>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, /* GICD */
<0x0b002000 0x2000>, /* GICC */
<0x0b001000 0x1000>, /* GICH */
<0x0b004000 0x2000>; /* GICV */
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0b00a000 0x1ffa>;
v2m0: v2m@0 {
compatible = "arm,gic-v2m-frame";
reg = <0x00000000 0xff8>;
msi-controller;
};
v2m1: v2m@1000 {
compatible = "arm,gic-v2m-frame";
reg = <0x00001000 0xff8>;
msi-controller;
};
};
timer@b120000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0b120000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
frame@b120000 {
reg = <0x0b121000 0x1000>,
<0x0b122000 0x1000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <0>;
};
frame@b123000 {
reg = <0xb123000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <1>;
status = "disabled";
};
frame@b124000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b124000 0x1000>;
status = "disabled";
};
frame@b125000 {
reg = <0x0b125000 0x1000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <3>;
status = "disabled";
};
frame@b126000 {
reg = <0x0b126000 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <4>;
status = "disabled";
};
frame@b127000 {
reg = <0x0b127000 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <5>;
status = "disabled";
};
frame@b128000 {
reg = <0x0b128000 0x1000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <6>;
status = "disabled";
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};

78
arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi Normal file
View File

@ -0,0 +1,78 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* IPQ5332 RDP board common device tree source
*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "ipq5332.dtsi"
/ {
aliases {
serial0 = &blsp1_uart0;
};
chosen {
stdout-path = "serial0";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&gpio_keys_default>;
pinctrl-names = "default";
button-wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&gpio_leds_default>;
pinctrl-names = "default";
led-0 {
gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tx";
default-state = "off";
};
};
};
&blsp1_uart0 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&sleep_clk {
clock-frequency = <32000>;
};
&xo_board {
clock-frequency = <24000000>;
};
/* PINCTRL */
&tlmm {
gpio_keys_default: gpio-keys-default-state {
pins = "gpio35";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
gpio_leds_default: gpio-leds-default-state {
pins = "gpio36";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
};

26
arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
View File

@ -7,25 +7,11 @@
/dts-v1/;
#include "ipq5332.dtsi"
#include "ipq5332-rdp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2";
compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332";
aliases {
serial0 = &blsp1_uart0;
};
chosen {
stdout-path = "serial0";
};
};
&blsp1_uart0 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&blsp1_i2c1 {
@ -46,16 +32,6 @@
status = "okay";
};
&sleep_clk {
clock-frequency = <32000>;
};
&xo_board {
clock-frequency = <24000000>;
};
/* PINCTRL */
&tlmm {
i2c_1_pins: i2c-1-state {
pins = "gpio29", "gpio30";

26
arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts
View File

@ -7,25 +7,11 @@
/dts-v1/;
#include "ipq5332.dtsi"
#include "ipq5332-rdp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ5332 MI01.3";
compatible = "qcom,ipq5332-ap-mi01.3", "qcom,ipq5332";
aliases {
serial0 = &blsp1_uart0;
};
chosen {
stdout-path = "serial0";
};
};
&blsp1_uart0 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&blsp1_i2c1 {
@ -60,16 +46,6 @@
status = "okay";
};
&sleep_clk {
clock-frequency = <32000>;
};
&xo_board {
clock-frequency = <24000000>;
};
/* PINCTRL */
&tlmm {
i2c_1_pins: i2c-1-state {
pins = "gpio29", "gpio30";

24
arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
View File

@ -7,25 +7,11 @@
/dts-v1/;
#include "ipq5332.dtsi"
#include "ipq5332-rdp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ5332 MI01.6";
compatible = "qcom,ipq5332-ap-mi01.6", "qcom,ipq5332";
aliases {
serial0 = &blsp1_uart0;
};
chosen {
stdout-path = "serial0";
};
};
&blsp1_uart0 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&blsp1_spi0 {
@ -53,14 +39,6 @@
status = "okay";
};
&sleep_clk {
clock-frequency = <32000>;
};
&xo_board {
clock-frequency = <24000000>;
};
/* PINCTRL */
&tlmm {

47
arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts
View File

@ -7,41 +7,11 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "ipq5332.dtsi"
#include "ipq5332-rdp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ5332 MI01.9";
compatible = "qcom,ipq5332-ap-mi01.9", "qcom,ipq5332";
aliases {
serial0 = &blsp1_uart0;
};
chosen {
stdout-path = "serial0";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&gpio_keys_default_state>;
pinctrl-names = "default";
button-wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
debounce-interval = <60>;
};
};
};
&blsp1_uart0 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&blsp1_i2c1 {
@ -62,24 +32,9 @@
status = "okay";
};
&sleep_clk {
clock-frequency = <32000>;
};
&xo_board {
clock-frequency = <24000000>;
};
/* PINCTRL */
&tlmm {
gpio_keys_default_state: gpio-keys-default-state {
pins = "gpio35";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
i2c_1_pins: i2c-1-state {
pins = "gpio29", "gpio30";
function = "blsp1_i2c0";

48
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View File

@ -146,6 +146,32 @@
method = "smc";
};
rpm: remoteproc {
compatible = "qcom,ipq6018-rpm-proc", "qcom,rpm-proc";
glink-edge {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-ipq6018";
qcom,glink-channels = "rpm_requests";
regulators {
compatible = "qcom,rpm-mp5496-regulators";
ipq6018_s2: s2 {
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1062500>;
regulator-always-on;
};
};
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@ -182,28 +208,6 @@
};
};
rpm-glink {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-ipq6018";
qcom,glink-channels = "rpm_requests";
regulators {
compatible = "qcom,rpm-mp5496-regulators";
ipq6018_s2: s2 {
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1062500>;
regulator-always-on;
};
};
};
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_region>;

8
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View File

@ -794,10 +794,10 @@
pcie1: pci@10000000 {
compatible = "qcom,pcie-ipq8074";
reg = <0x10000000 0xf1d>,
<0x10000f20 0xa8>,
<0x00088000 0x2000>,
<0x10100000 0x1000>;
reg = <0x10000000 0xf1d>,
<0x10000f20 0xa8>,
<0x00088000 0x2000>,
<0x10100000 0x1000>;
reg-names = "dbi", "elbi", "parf", "config";
device_type = "pci";
linux,pci-domain = <1>;

48
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
View File

@ -21,6 +21,24 @@
chosen {
stdout-path = "serial0:115200n8";
};
regulator_fixed_3p3: s3300 {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-name = "fixed_3p3";
};
regulator_fixed_0p925: s0925 {
compatible = "regulator-fixed";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <925000>;
regulator-boot-on;
regulator-always-on;
regulator-name = "fixed_0p925";
};
};
&blsp1_uart2 {
@ -45,6 +63,13 @@
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1075000>;
};
mp5496_l2: l2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
};
};
@ -98,6 +123,29 @@
};
};
&usb_0_dwc3 {
dr_mode = "host";
};
&usb_0_qmpphy {
vdda-pll-supply = <&mp5496_l2>;
vdda-phy-supply = <&regulator_fixed_0p925>;
status = "okay";
};
&usb_0_qusbphy {
vdd-supply = <&regulator_fixed_0p925>;
vdda-pll-supply = <&mp5496_l2>;
vdda-phy-dpdm-supply = <&regulator_fixed_3p3>;
status = "okay";
};
&usb3 {
status = "okay";
};
&xo_board_clk {
clock-frequency = <24000000>;
};

182
arch/arm64/boot/dts/qcom/ipq9574.dtsi
View File

@ -10,6 +10,7 @@
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@ -42,6 +43,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq9574_s1>;
#cooling-cells = <2>;
};
CPU1: cpu@1 {
@ -54,6 +56,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq9574_s1>;
#cooling-cells = <2>;
};
CPU2: cpu@2 {
@ -66,6 +69,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq9574_s1>;
#cooling-cells = <2>;
};
CPU3: cpu@3 {
@ -78,6 +82,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq9574_s1>;
#cooling-cells = <2>;
};
L2_0: l2-cache {
@ -151,6 +156,22 @@
method = "smc";
};
rpm: remoteproc {
compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc";
glink-edge {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-ipq9574";
qcom,glink-channels = "rpm_requests";
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@ -179,18 +200,6 @@
};
};
rpm-glink {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-ipq9574";
qcom,glink-channels = "rpm_requests";
};
};
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
@ -401,6 +410,8 @@
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
assigned-clock-rates = <50000000>;
dmas = <&blsp_dma 14>, <&blsp_dma 15>;
dma-names = "tx", "rx";
status = "disabled";
@ -429,6 +440,8 @@
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
assigned-clock-rates = <50000000>;
dmas = <&blsp_dma 16>, <&blsp_dma 17>;
dma-names = "tx", "rx";
status = "disabled";
@ -457,6 +470,8 @@
clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
assigned-clock-rates = <50000000>;
dmas = <&blsp_dma 18>, <&blsp_dma 19>;
dma-names = "tx", "rx";
status = "disabled";
@ -486,6 +501,8 @@
clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
assigned-clock-rates = <50000000>;
dmas = <&blsp_dma 20>, <&blsp_dma 21>;
dma-names = "tx", "rx";
status = "disabled";
@ -505,6 +522,91 @@
status = "disabled";
};
usb_0_qusbphy: phy@7b000 {
compatible = "qcom,ipq9574-qusb2-phy";
reg = <0x0007b000 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
<&xo_board_clk>;
clock-names = "cfg_ahb",
"ref";
resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
status = "disabled";
};
usb_0_qmpphy: phy@7d000 {
compatible = "qcom,ipq9574-qmp-usb3-phy";
reg = <0x0007d000 0xa00>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB0_AUX_CLK>,
<&xo_board_clk>,
<&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB0_PIPE_CLK>;
clock-names = "aux",
"ref",
"cfg_ahb",
"pipe";
resets = <&gcc GCC_USB0_PHY_BCR>,
<&gcc GCC_USB3PHY_0_PHY_BCR>;
reset-names = "phy",
"phy_phy";
#clock-cells = <0>;
clock-output-names = "usb0_pipe_clk";
status = "disabled";
};
usb3: usb@8af8800 {
compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
reg = <0x08af8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_SNOC_USB_CLK>,
<&gcc GCC_USB0_MASTER_CLK>,
<&gcc GCC_ANOC_USB_AXI_CLK>,
<&gcc GCC_USB0_SLEEP_CLK>,
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
clock-names = "cfg_noc",
"core",
"iface",
"sleep",
"mock_utmi";
assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
assigned-clock-rates = <200000000>,
<24000000>;
interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event";
resets = <&gcc GCC_USB_BCR>;
status = "disabled";
usb_0_dwc3: usb@8a00000 {
compatible = "snps,dwc3";
reg = <0x8a00000 0xcd00>;
clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
clock-names = "ref";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
tx-fifo-resize;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
};
};
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, /* GICD */
@ -727,18 +829,28 @@
thermal-sensors = <&tsens 10>;
trips {
cpu-critical {
cpu0_crit: cpu-critical {
temperature = <120000>;
hysteresis = <10000>;
type = "critical";
};
cpu-passive {
cpu0_alert: cpu-passive {
temperature = <110000>;
hysteresis = <1000>;
type = "passive";
};
};
cooling-maps {
map0 {
trip = <&cpu0_alert>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu1-thermal {
@ -747,18 +859,28 @@
thermal-sensors = <&tsens 11>;
trips {
cpu-critical {
cpu1_crit: cpu-critical {
temperature = <120000>;
hysteresis = <10000>;
type = "critical";
};
cpu-passive {
cpu1_alert: cpu-passive {
temperature = <110000>;
hysteresis = <1000>;
type = "passive";
};
};
cooling-maps {
map0 {
trip = <&cpu1_alert>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu2-thermal {
@ -767,18 +889,28 @@
thermal-sensors = <&tsens 12>;
trips {
cpu-critical {
cpu2_crit: cpu-critical {
temperature = <120000>;
hysteresis = <10000>;
type = "critical";
};
cpu-passive {
cpu2_alert: cpu-passive {
temperature = <110000>;
hysteresis = <1000>;
type = "passive";
};
};
cooling-maps {
map0 {
trip = <&cpu2_alert>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu3-thermal {
@ -787,18 +919,28 @@
thermal-sensors = <&tsens 13>;
trips {
cpu-critical {
cpu3_crit: cpu-critical {
temperature = <120000>;
hysteresis = <10000>;
type = "critical";
};
cpu-passive {
cpu3_alert: cpu-passive {
temperature = <110000>;
hysteresis = <1000>;
type = "passive";
};
};
cooling-maps {
map0 {
trip = <&cpu3_alert>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
wcss-phyb-thermal {

2
arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts
View File

@ -48,7 +48,7 @@
usb_id: usb-id {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>;
id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_id_default>;
};

2
arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts
View File

@ -52,7 +52,7 @@
usb_id: usb-id {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&tlmm 69 GPIO_ACTIVE_HIGH>;
id-gpios = <&tlmm 69 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_id_default>;
};

2
arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts
View File

@ -75,7 +75,7 @@
usb_id: usb-id {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>;
id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&usb_id_default>;
pinctrl-names = "default";
};

2
arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts
View File

@ -80,7 +80,7 @@
usb_id: usb-id {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&tlmm 117 GPIO_ACTIVE_HIGH>;
id-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_id_default>;
};

2
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts
View File

@ -165,7 +165,7 @@
pinctrl-0 = <&light_int_default>;
vdd-supply = <&pm8916_l17>;
vio-supply = <&pm8916_l6>;
vddio-supply = <&pm8916_l6>;
};
gyroscope@68 {

2
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts
View File

@ -68,7 +68,7 @@
usb_id: usb-id {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>;
id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_id_default>;
};

1
arch/arm64/boot/dts/qcom/msm8916-mtp.dts
View File

@ -10,6 +10,7 @@
/ {
model = "Qualcomm Technologies, Inc. MSM 8916 MTP";
compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp/1", "qcom,msm8916";
chassis-type = "handset";
aliases {
serial0 = &blsp_uart2;

21
arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi
View File

@ -42,10 +42,27 @@
&blsp_i2c2 {
/* lis2hh12 accelerometer instead of BMC150 */
status = "disabled";
/delete-node/ accelerometer@10;
/delete-node/ magnetometer@12;
accelerometer@1d {
compatible = "st,lis2hh12";
reg = <0x1d>;
interrupt-parent = <&tlmm>;
interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
vdd-supply = <&pm8916_l5>;
vddio-supply = <&pm8916_l5>;
st,drdy-int-pin = <1>;
mount-matrix = "1", "0", "0",
"0", "-1", "0",
"0", "0", "1";
pinctrl-0 = <&accel_int_default>;
pinctrl-names = "default";
};
};
&reg_motor_vdd {

20
arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts
View File

@ -22,3 +22,23 @@
compatible = "samsung,e5", "qcom,msm8916";
chassis-type = "handset";
};
&blsp_i2c5 {
status = "okay";
touchscreen@48 {
compatible = "melfas,mms345l";
reg = <0x48>;
interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>;
touchscreen-size-x = <720>;
touchscreen-size-y = <1280>;
avdd-supply = <&reg_vdd_tsp_a>;
vdd-supply = <&pm8916_l6>;
pinctrl-0 = <&ts_int_default>;
pinctrl-names = "default";
};
};

1
arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi
View File

@ -101,7 +101,6 @@
interrupt-parent = <&tlmm>;
interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "INT1";
st,drdy-int-pin = <1>;
mount-matrix = "0", "1", "0",

29
arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi
View File

@ -86,6 +86,26 @@
};
};
&blsp_i2c5 {
status = "okay";
touchscreen: touchscreen@50 {
compatible = "imagis,ist3038c";
reg = <0x50>;
interrupt-parent = <&tlmm>;
interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
touchscreen-size-x = <720>;
touchscreen-size-y = <1280>;
vddio-supply = <&pm8916_l6>;
pinctrl-0 = <&tsp_int_default>;
pinctrl-names = "default";
};
};
&blsp_uart2 {
status = "okay";
};
@ -162,6 +182,15 @@
sdc2_cd_default: sdc2-cd-default-state {
pins = "gpio38";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tsp_int_default: tsp-int-default-state {
pins = "gpio13";
function = "gpio";
drive-strength = <2>;
bias-disable;
};

8
arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts
View File

@ -10,6 +10,14 @@
chassis-type = "handset";
};
&blsp_i2c5 {
status = "disabled";
};
&touchscreen {
/* FIXME: Missing sm5703-mfd driver to power up vdd-supply */
};
&usb_hs_phy {
qcom,init-seq = /bits/ 8 <0x1 0x19 0x2 0x0b>;
};

26
arch/arm64/boot/dts/qcom/msm8916-samsung-j5x.dts
View File

@ -8,12 +8,38 @@
model = "Samsung Galaxy J5 (2016)";
compatible = "samsung,j5x", "qcom,msm8916";
chassis-type = "handset";
reg_vdd_tsp_a: regulator-vdd-tsp-a {
compatible = "regulator-fixed";
regulator-name = "vdd_tsp_a";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&tlmm 108 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&tsp_ldo_en_default>;
pinctrl-names = "default";
};
};
&muic {
interrupts = <121 IRQ_TYPE_EDGE_FALLING>;
};
&touchscreen {
vdd-supply = <&reg_vdd_tsp_a>;
};
&tlmm {
tsp_ldo_en_default: tsp-ldo-en-default-state {
pins = "gpio108";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
&muic_int_default {
pins = "gpio121";
};

70
arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts
View File

@ -142,6 +142,12 @@
pinctrl-names = "default";
pinctrl-0 = <&muic_irq_default>;
usb_con: connector {
compatible = "usb-b-connector";
label = "micro-USB";
type = "micro";
};
};
};
@ -199,6 +205,15 @@
pinctrl-0 = <&nfc_default>;
};
};
battery: battery {
compatible = "simple-battery";
precharge-current-microamp = <450000>;
constant-charge-current-max-microamp = <1000000>;
charge-term-current-microamp = <150000>;
precharge-upper-limit-microvolt = <3500000>;
constant-charge-voltage-max-microvolt = <4350000>;
};
};
&blsp_i2c2 {
@ -219,16 +234,16 @@
compatible = "yamaha,yas537";
reg = <0x2e>;
mount-matrix = "0", "1", "0",
"1", "0", "0",
"0", "0", "-1";
mount-matrix = "0", "1", "0",
"1", "0", "0",
"0", "0", "-1";
};
};
&blsp_i2c4 {
status = "okay";
battery@35 {
fuel-gauge@35 {
compatible = "richtek,rt5033-battery";
reg = <0x35>;
@ -237,6 +252,8 @@
pinctrl-names = "default";
pinctrl-0 = <&fg_alert_default>;
power-supplies = <&rt5033_charger>;
};
};
@ -261,6 +278,43 @@
};
};
&blsp_i2c6 {
status = "okay";
pmic@34 {
compatible = "richtek,rt5033";
reg = <0x34>;
interrupt-parent = <&tlmm>;
interrupts = <62 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_default>;
regulators {
rt5033_reg_safe_ldo: SAFE_LDO {
regulator-min-microvolt = <4900000>;
regulator-max-microvolt = <4900000>;
regulator-always-on;
};
rt5033_reg_ldo: LDO {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
rt5033_reg_buck: BUCK {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
};
rt5033_charger: charger {
compatible = "richtek,rt5033-charger";
monitored-battery = <&battery>;
richtek,usb-connector = <&usb_con>;
};
};
};
&blsp_uart2 {
status = "okay";
};
@ -387,6 +441,14 @@
bias-disable;
};
pmic_int_default: pmic-int-default-state {
pins = "gpio62";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tkey_default: tkey-default-state {
pins = "gpio98";
function = "gpio";

2
arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts
View File

@ -56,7 +56,7 @@
usb_id: usb-id {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>;
id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_id_default>;
};

14
arch/arm64/boot/dts/qcom/msm8916.dtsi
View File

@ -282,10 +282,10 @@
};
};
smd {
compatible = "qcom,smd";
rpm: remoteproc {
compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc";
rpm {
smd-edge {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
@ -1712,6 +1712,14 @@
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
};
};

495
arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts Normal file
View File

@ -0,0 +1,495 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "msm8939-pm8916.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "Samsung Galaxy A7 (2015)";
compatible = "samsung,a7", "qcom,msm8939";
chassis-type = "handset";
aliases {
mmc0 = &sdhc_1; /* SDC1 eMMC slot */
mmc1 = &sdhc_2; /* SDC2 SD card slot */
serial0 = &blsp_uart2;
};
chosen {
stdout-path = "serial0";
};
reserved-memory {
/* Additional memory used by Samsung firmware modifications */
tz-apps@85500000 {
reg = <0x0 0x85500000 0x0 0xb00000>;
no-map;
};
};
gpio-hall-sensor {
compatible = "gpio-keys";
pinctrl-0 = <&gpio_hall_sensor_default>;
pinctrl-names = "default";
label = "GPIO Hall Effect Sensor";
event-hall-sensor {
label = "Hall Effect Sensor";
gpios = <&tlmm 52 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
linux,can-disable;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&gpio_keys_default>;
pinctrl-names = "default";
label = "GPIO Buttons";
button-volume-up {
label = "Volume Up";
gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
button-home {
label = "Home";
gpios = <&tlmm 109 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOMEPAGE>;
};
};
i2c-fg {
compatible = "i2c-gpio";
sda-gpios = <&tlmm 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&tlmm 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
pinctrl-0 = <&fg_i2c_default>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
battery@35 {
compatible = "richtek,rt5033-battery";
reg = <0x35>;
interrupt-parent = <&tlmm>;
interrupts = <121 IRQ_TYPE_EDGE_BOTH>;
pinctrl-0 = <&fg_alert_default>;
pinctrl-names = "default";
};
};
i2c-nfc {
compatible = "i2c-gpio";
sda-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
pinctrl-0 = <&nfc_i2c_default>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
nfc@2b {
compatible = "nxp,pn547", "nxp,nxp-nci-i2c";
reg = <0x2b>;
interrupt-parent = <&tlmm>;
interrupts = <21 IRQ_TYPE_EDGE_RISING>;
enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>;
firmware-gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&nfc_default>;
pinctrl-names = "default";
};
};
i2c-sensor {
compatible = "i2c-gpio";
sda-gpios = <&tlmm 84 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&tlmm 85 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
pinctrl-0 = <&sensor_i2c_default>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
accelerometer: accelerometer@10 {
compatible = "bosch,bmc150_accel";
reg = <0x10>;
interrupt-parent = <&tlmm>;
interrupts = <115 IRQ_TYPE_EDGE_RISING>;
vdd-supply = <&pm8916_l17>;
vddio-supply = <&pm8916_l5>;
pinctrl-0 = <&accel_int_default>;
pinctrl-names = "default";
mount-matrix = "-1", "0", "0",
"0", "-1", "0",
"0", "0", "1";
};
magnetometer@12 {
compatible = "bosch,bmc150_magn";
reg = <0x12>;
vdd-supply = <&pm8916_l17>;
vddio-supply = <&pm8916_l5>;
};
};
i2c-tkey {
compatible = "i2c-gpio";
sda-gpios = <&tlmm 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&tlmm 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
pinctrl-0 = <&tkey_i2c_default>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
touchkey@20 {
/* Note: Actually an ABOV MCU that implements same interface */
compatible = "coreriver,tc360-touchkey";
reg = <0x20>;
interrupt-parent = <&tlmm>;
interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
vcc-supply = <&reg_touch_key>;
vdd-supply = <&reg_keyled>;
vddio-supply = <&pm8916_l6>;
linux,keycodes = <KEY_APPSELECT KEY_BACK>;
pinctrl-0 = <&tkey_default>;
pinctrl-names = "default";
};
};
pwm_vibrator: pwm-vibrator {
compatible = "clk-pwm";
#pwm-cells = <2>;
clocks = <&gcc GCC_GP2_CLK>;
pinctrl-0 = <&motor_pwm_default>;
pinctrl-names = "default";
};
reg_keyled: regulator-keyled {
compatible = "regulator-fixed";
regulator-name = "keyled";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
/* NOTE: On some variants e.g. SM-A700FD it's GPIO 91 */
gpio = <&tlmm 100 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&tkey_led_en_default>;
pinctrl-names = "default";
};
reg_touch_key: regulator-touch-key {
compatible = "regulator-fixed";
regulator-name = "touch_key";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&tlmm 56 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&tkey_en_default>;
pinctrl-names = "default";
};
reg_tsp_vdd: regulator-tsp-vdd {
compatible = "regulator-fixed";
regulator-name = "tsp_vdd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&pm8916_s4>;
gpio = <&tlmm 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&reg_tsp_io_en_default>;
pinctrl-names = "default";
};
reg_vdd_tsp: regulator-vdd-tsp {
compatible = "regulator-fixed";
regulator-name = "vdd_tsp";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&reg_tsp_en_default>;
pinctrl-names = "default";
};
reg_vibrator: regulator-vibrator {
compatible = "regulator-fixed";
regulator-name = "motor_en";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&motor_en_default>;
pinctrl-names = "default";
};
vibrator {
compatible = "pwm-vibrator";
pwms = <&pwm_vibrator 0 100000>;
pwm-names = "enable";
vcc-supply = <&reg_vibrator>;
};
};
&blsp_i2c1 {
status = "okay";
muic: extcon@25 {
compatible = "siliconmitus,sm5502-muic";
reg = <0x25>;
interrupt-parent = <&tlmm>;
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&muic_int_default>;
pinctrl-names = "default";
};
};
&blsp_i2c5 {
status = "okay";
touchscreen@24 {
compatible = "cypress,tt21000";
reg = <0x24>;
interrupt-parent = <&tlmm>;
interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
vdd-supply = <&reg_vdd_tsp>;
vddio-supply = <&reg_tsp_vdd>;
pinctrl-0 = <&tsp_int_default>;
pinctrl-names = "default";
};
};
&blsp_uart2 {
status = "okay";
};
&pm8916_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&pm8916_rpm_regulators {
pm8916_l17: l17 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
};
&sdhc_1 {
status = "okay";
};
&sdhc_2 {
pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
pinctrl-names = "default", "sleep";
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
status = "okay";
};
&usb {
extcon = <&muic>, <&muic>;
status = "okay";
};
&usb_hs_phy {
extcon = <&muic>;
};
&wcnss {
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3660b";
};
&tlmm {
accel_int_default: accel-int-default-state {
pins = "gpio115";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
fg_alert_default: fg-alert-default-state {
pins = "gpio121";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
fg_i2c_default: fg-i2c-default-state {
pins = "gpio105", "gpio106";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
gpio_hall_sensor_default: gpio-hall-sensor-default-state {
pins = "gpio52";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
gpio_keys_default: gpio-keys-default-state {
pins = "gpio107", "gpio109";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
motor_en_default: motor-en-default-state {
pins = "gpio86";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
motor_pwm_default: motor-pwm-default-state {
pins = "gpio50";
function = "gcc_gp2_clk_a";
};
muic_int_default: muic-int-default-state {
pins = "gpio12";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
nfc_default: nfc-default-state {
irq-pins {
pins = "gpio21";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
nfc-pins {
pins = "gpio49", "gpio116";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
nfc_i2c_default: nfc-i2c-default-state {
pins = "gpio0", "gpio1";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
reg_tsp_en_default: reg-tsp-en-default-state {
pins = "gpio73";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
reg_tsp_io_en_default: reg-tsp-io-en-default-state {
pins = "gpio8";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
sdc2_cd_default: sdc2-cd-default-state {
pins = "gpio38";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
sensor_i2c_default: sensor-i2c-default-state {
pins = "gpio84", "gpio85";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tkey_default: tkey-default-state {
pins = "gpio20";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tkey_en_default: tkey-en-default-state {
pins = "gpio56";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tkey_i2c_default: tkey-i2c-default-state {
pins = "gpio16", "gpio17";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tkey_led_en_default: tkey-led-en-default-state {
pins = "gpio100";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tsp_int_default: tsp-int-default-state {
pins = "gpio13";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};

3
arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts
View File

@ -16,6 +16,7 @@
/ {
model = "Sony Xperia M4 Aqua";
compatible = "sony,kanuti-tulip", "qcom,msm8939";
chassis-type = "handset";
qcom,board-id = <QCOM_BOARD_ID_MTP 0>;
qcom,msm-id = <QCOM_ID_MSM8939 0>, <QCOM_ID_MSM8939 0x30000>;
@ -32,7 +33,7 @@
usb_id: usb-id {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>;
id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&usb_id_default>;
pinctrl-names = "default";
};

132
arch/arm64/boot/dts/qcom/msm8939.dtsi
View File

@ -55,6 +55,7 @@
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
@ -111,6 +112,7 @@
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
@ -155,7 +157,7 @@
idle-states {
CPU_SLEEP_0: cpu-sleep-0 {
compatible ="qcom,idle-state-spc", "arm,idle-state";
compatible = "arm,idle-state";
entry-latency-us = <130>;
exit-latency-us = <150>;
min-residency-us = <2000>;
@ -240,6 +242,62 @@
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
};
rpm: remoteproc {
compatible = "qcom,msm8936-rpm-proc", "qcom,rpm-proc";
smd-edge {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs1_mbox 8 0>;
qcom,smd-edge = <15>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8936";
qcom,smd-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc";
#clock-cells = <1>;
clock-names = "xo";
clocks = <&xo_board>;
};
rpmpd: power-controller {
compatible = "qcom,msm8939-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp_ret: opp1 {
opp-level = <1>;
};
rpmpd_opp_svs_krait: opp2 {
opp-level = <2>;
};
rpmpd_opp_svs_soc: opp3 {
opp-level = <3>;
};
rpmpd_opp_nom: opp4 {
opp-level = <4>;
};
rpmpd_opp_turbo: opp5 {
opp-level = <5>;
};
rpmpd_opp_super_turbo: opp6 {
opp-level = <6>;
};
};
};
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@ -308,62 +366,6 @@
};
};
smd {
compatible = "qcom,smd";
rpm {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs1_mbox 8 0>;
qcom,smd-edge = <15>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8936";
qcom,smd-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc";
#clock-cells = <1>;
clock-names = "xo";
clocks = <&xo_board>;
};
rpmpd: power-controller {
compatible = "qcom,msm8939-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp_ret: opp1 {
opp-level = <1>;
};
rpmpd_opp_svs_krait: opp2 {
opp-level = <2>;
};
rpmpd_opp_svs_soc: opp3 {
opp-level = <3>;
};
rpmpd_opp_nom: opp4 {
opp-level = <4>;
};
rpmpd_opp_turbo: opp5 {
opp-level = <5>;
};
rpmpd_opp_super_turbo: opp6 {
opp-level = <6>;
};
};
};
};
};
};
smp2p-hexagon {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
@ -386,8 +388,6 @@
interrupt-controller;
#interrupt-cells = <2>;
#address-cells = <0>;
#size-cells = <0>;
};
};
@ -1644,7 +1644,7 @@
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "core", "xo";
clock-names = "iface", "core", "xo";
resets = <&gcc GCC_SDCC2_BCR>;
pinctrl-0 = <&sdc2_default>;
pinctrl-1 = <&sdc2_sleep>;
@ -1731,7 +1731,7 @@
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-names = "core", "iface";
dmas = <&blsp_dma 6>, <&blsp_dma 7>;
dma-names = "tx", "rx";
pinctrl-0 = <&blsp_i2c2_default>;
@ -1765,7 +1765,7 @@
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-names = "core", "iface";
dmas = <&blsp_dma 8>, <&blsp_dma 9>;
dma-names = "tx", "rx";
pinctrl-0 = <&blsp_i2c3_default>;
@ -1799,7 +1799,7 @@
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-names = "core", "iface";
dmas = <&blsp_dma 10>, <&blsp_dma 11>;
dma-names = "tx", "rx";
pinctrl-0 = <&blsp_i2c4_default>;
@ -1833,7 +1833,7 @@
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-names = "core", "iface";
dmas = <&blsp_dma 12>, <&blsp_dma 13>;
dma-names = "tx", "rx";
pinctrl-0 = <&blsp_i2c5_default>;
@ -1867,7 +1867,7 @@
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-names = "core", "iface";
dmas = <&blsp_dma 14>, <&blsp_dma 15>;
dma-names = "tx", "rx";
pinctrl-0 = <&blsp_i2c6_default>;
@ -1975,7 +1975,7 @@
};
smd-edge {
interrupts = <GIC_SPI 142 1>;
interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs1_mbox 8 17>;
qcom,smd-edge = <6>;
qcom,remote-pid = <4>;

4
arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts
View File

@ -17,7 +17,7 @@
compatible = "xiaomi,daisy", "qcom,msm8953";
chassis-type = "handset";
qcom,msm-id = <293 0>;
qcom,board-id= <0x1000b 0x9>;
qcom,board-id = <0x1000b 0x9>;
chosen {
#address-cells = <2>;
@ -125,7 +125,7 @@
vmon-slot-no = <1>;
imon-slot-no = <1>;
interleave_mode = <0>;
maxim,interleave-mode;
#sound-dai-cells = <0>;
};

2
arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts
View File

@ -96,7 +96,7 @@
vmon-slot-no = <1>;
imon-slot-no = <1>;
#sound-dai-cells = <1>;
#sound-dai-cells = <0>;
};
led-controller@45 {

3
arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts
View File

@ -20,7 +20,7 @@
compatible = "xiaomi,vince", "qcom,msm8953";
chassis-type = "handset";
qcom,msm-id = <293 0>;
qcom,board-id= <0x1000b 0x08>;
qcom,board-id = <0x1000b 0x08>;
gpio-keys {
compatible = "gpio-keys";
@ -132,7 +132,6 @@
touchscreen@20 {
reg = <0x20>;
compatible = "syna,rmi4-i2c";
interrupts-parent = <&tlmm>;
interrupts-extended = <&tlmm 65 IRQ_TYPE_EDGE_FALLING>;
#address-cells = <1>;

136
arch/arm64/boot/dts/qcom/msm8953.dtsi
View File

@ -190,6 +190,74 @@
method = "smc";
};
rpm: remoteproc {
compatible = "qcom,msm8953-rpm-proc", "qcom,rpm-proc";
smd-edge {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8953";
qcom,smd-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc";
clocks = <&xo_board>;
clock-names = "xo";
#clock-cells = <1>;
};
rpmpd: power-controller {
compatible = "qcom,msm8953-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp_ret: opp1 {
opp-level = <RPM_SMD_LEVEL_RETENTION>;
};
rpmpd_opp_ret_plus: opp2 {
opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
};
rpmpd_opp_min_svs: opp3 {
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
};
rpmpd_opp_low_svs: opp4 {
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
};
rpmpd_opp_svs: opp5 {
opp-level = <RPM_SMD_LEVEL_SVS>;
};
rpmpd_opp_svs_plus: opp6 {
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
};
rpmpd_opp_nom: opp7 {
opp-level = <RPM_SMD_LEVEL_NOM>;
};
rpmpd_opp_nom_plus: opp8 {
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
};
rpmpd_opp_turbo: opp9 {
opp-level = <RPM_SMD_LEVEL_TURBO>;
};
};
};
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@ -263,74 +331,6 @@
};
};
smd {
compatible = "qcom,smd";
rpm {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8953";
qcom,smd-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc";
clocks = <&xo_board>;
clock-names = "xo";
#clock-cells = <1>;
};
rpmpd: power-controller {
compatible = "qcom,msm8953-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp_ret: opp1 {
opp-level = <RPM_SMD_LEVEL_RETENTION>;
};
rpmpd_opp_ret_plus: opp2 {
opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
};
rpmpd_opp_min_svs: opp3 {
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
};
rpmpd_opp_low_svs: opp4 {
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
};
rpmpd_opp_svs: opp5 {
opp-level = <RPM_SMD_LEVEL_SVS>;
};
rpmpd_opp_svs_plus: opp6 {
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
};
rpmpd_opp_nom: opp7 {
opp-level = <RPM_SMD_LEVEL_NOM>;
};
rpmpd_opp_nom_plus: opp8 {
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
};
rpmpd_opp_turbo: opp9 {
opp-level = <RPM_SMD_LEVEL_TURBO>;
};
};
};
};
};
};
smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;

154
arch/arm64/boot/dts/qcom/msm8976.dtsi
View File

@ -232,6 +232,82 @@
method = "smc";
};
rpm: remoteproc {
compatible = "qcom,msm8976-rpm-proc", "qcom,rpm-proc";
smd-edge {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8976";
qcom,smd-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc";
clocks = <&xo_board>;
clock-names = "xo";
#clock-cells = <1>;
};
rpmpd: power-controller {
compatible = "qcom,msm8976-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp_ret: opp1 {
opp-level = <RPM_SMD_LEVEL_RETENTION>;
};
rpmpd_opp_ret_plus: opp2 {
opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
};
rpmpd_opp_min_svs: opp3 {
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
};
rpmpd_opp_low_svs: opp4 {
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
};
rpmpd_opp_svs: opp5 {
opp-level = <RPM_SMD_LEVEL_SVS>;
};
rpmpd_opp_svs_plus: opp6 {
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
};
rpmpd_opp_nom: opp7 {
opp-level = <RPM_SMD_LEVEL_NOM>;
};
rpmpd_opp_nom_plus: opp8 {
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
};
rpmpd_opp_turbo: opp9 {
opp-level = <RPM_SMD_LEVEL_TURBO>;
};
rpmpd_opp_turbo_no_cpr: opp10 {
opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
};
rpmpd_opp_turbo_high: opp111 {
opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>;
};
};
};
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@ -346,82 +422,6 @@
};
};
smd {
compatible = "qcom,smd";
rpm {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8976";
qcom,smd-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc";
clocks = <&xo_board>;
clock-names = "xo";
#clock-cells = <1>;
};
rpmpd: power-controller {
compatible = "qcom,msm8976-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp_ret: opp1 {
opp-level = <RPM_SMD_LEVEL_RETENTION>;
};
rpmpd_opp_ret_plus: opp2 {
opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
};
rpmpd_opp_min_svs: opp3 {
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
};
rpmpd_opp_low_svs: opp4 {
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
};
rpmpd_opp_svs: opp5 {
opp-level = <RPM_SMD_LEVEL_SVS>;
};
rpmpd_opp_svs_plus: opp6 {
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
};
rpmpd_opp_nom: opp7 {
opp-level = <RPM_SMD_LEVEL_NOM>;
};
rpmpd_opp_nom_plus: opp8 {
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
};
rpmpd_opp_turbo: opp9 {
opp-level = <RPM_SMD_LEVEL_TURBO>;
};
rpmpd_opp_turbo_no_cpr: opp10 {
opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
};
rpmpd_opp_turbo_high: opp111 {
opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>;
};
};
};
};
};
};
smsm {
compatible = "qcom,smsm";
@ -439,7 +439,7 @@
hexagon_smsm: hexagon@1 {
reg = <1>;
interrupts = <0 290 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;

101
arch/arm64/boot/dts/qcom/msm8994.dtsi
View File

@ -178,6 +178,56 @@
method = "hvc";
};
rpm: remoteproc {
compatible = "qcom,msm8994-rpm-proc", "qcom,rpm-proc";
smd-edge {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
qcom,remote-pid = <6>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8994";
qcom,smd-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc";
#clock-cells = <1>;
};
rpmpd: power-controller {
compatible = "qcom,msm8994-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp_ret: opp1 {
opp-level = <1>;
};
rpmpd_opp_svs_krait: opp2 {
opp-level = <2>;
};
rpmpd_opp_svs_soc: opp3 {
opp-level = <3>;
};
rpmpd_opp_nom: opp4 {
opp-level = <4>;
};
rpmpd_opp_turbo: opp5 {
opp-level = <5>;
};
rpmpd_opp_super_turbo: opp6 {
opp-level = <6>;
};
};
};
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@ -237,55 +287,6 @@
};
};
smd {
compatible = "qcom,smd";
rpm {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
qcom,remote-pid = <6>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8994";
qcom,smd-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc";
#clock-cells = <1>;
};
rpmpd: power-controller {
compatible = "qcom,msm8994-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp_ret: opp1 {
opp-level = <1>;
};
rpmpd_opp_svs_krait: opp2 {
opp-level = <2>;
};
rpmpd_opp_svs_soc: opp3 {
opp-level = <3>;
};
rpmpd_opp_nom: opp4 {
opp-level = <4>;
};
rpmpd_opp_turbo: opp5 {
opp-level = <5>;
};
rpmpd_opp_super_turbo: opp6 {
opp-level = <6>;
};
};
};
};
};
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
@ -455,7 +456,7 @@
usb@f9200000 {
compatible = "snps,dwc3";
reg = <0xf9200000 0xcc00>;
interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
maximum-speed = "high-speed";

1
arch/arm64/boot/dts/qcom/msm8996-mtp.dts
View File

@ -10,6 +10,7 @@
/ {
model = "Qualcomm Technologies, Inc. MSM 8996 MTP";
compatible = "qcom,msm8996-mtp", "qcom,msm8996";
chassis-type = "handset";
aliases {
serial0 = &blsp2_uart2;

2
arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dts
View File

@ -24,5 +24,5 @@
};
&usb3_id {
id-gpio = <&tlmm 24 GPIO_ACTIVE_LOW>;
id-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>;
};

2
arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
View File

@ -71,7 +71,7 @@
usb3_id: usb3-id {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&tlmm 25 GPIO_ACTIVE_LOW>;
id-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&usb_detect>;
};

8
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
View File

@ -187,10 +187,9 @@
&blsp2_i2c2 {
status = "okay";
label = "NFC_I2C";
clock-frequency = <400000>;
nfc: pn548@28 {
nfc: nfc@28 {
compatible = "nxp,nxp-nci-i2c";
reg = <0x28>;
@ -208,9 +207,8 @@
&blsp2_i2c3 {
status = "okay";
label = "TYPEC_I2C";
typec: tusb320l@47 {
typec: typec@47 {
compatible = "ti,tusb320l";
reg = <0x47>;
interrupt-parent = <&tlmm>;
@ -220,7 +218,7 @@
&blsp2_i2c6 {
status = "okay";
label = "MSM_TS_I2C";
/* MSM_TS */
};
&blsp1_uart2 {

2
arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts
View File

@ -82,7 +82,7 @@
#size-cells = <0>;
interrupt-parent = <&tlmm>;
interrupts = <125 IRQ_TYPE_LEVEL_LOW>;
vdda-supply = <&vreg_l6a_1p8>;
vio-supply = <&vreg_l6a_1p8>;
vdd-supply = <&vdd_3v2_tp>;
reset-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;

193
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interconnect/qcom,msm8996.h>
#include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,apr.h>
@ -49,6 +50,7 @@
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
clocks = <&kryocc 0>;
interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
@ -67,6 +69,7 @@
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
clocks = <&kryocc 0>;
interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
@ -80,6 +83,7 @@
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
clocks = <&kryocc 1>;
interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
next-level-cache = <&L2_1>;
@ -98,6 +102,7 @@
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
clocks = <&kryocc 1>;
interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
next-level-cache = <&L2_1>;
@ -149,91 +154,109 @@
opp-hz = /bits/ 64 <307200000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <307200>;
};
opp-422400000 {
opp-hz = /bits/ 64 <422400000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <307200>;
};
opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <307200>;
};
opp-556800000 {
opp-hz = /bits/ 64 <556800000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <307200>;
};
opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <384000>;
};
opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <460800>;
};
opp-844800000 {
opp-hz = /bits/ 64 <844800000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <537600>;
};
opp-960000000 {
opp-hz = /bits/ 64 <960000000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <672000>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <672000>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <825600>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <825600>;
};
opp-1228800000 {
opp-hz = /bits/ 64 <1228800000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <902400>;
};
opp-1324800000 {
opp-hz = /bits/ 64 <1324800000>;
opp-supported-hw = <0xd>;
clock-latency-ns = <200000>;
opp-peak-kBps = <1056000>;
};
opp-1363200000 {
opp-hz = /bits/ 64 <1363200000>;
opp-supported-hw = <0x2>;
clock-latency-ns = <200000>;
opp-peak-kBps = <1132800>;
};
opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>;
opp-supported-hw = <0xd>;
clock-latency-ns = <200000>;
opp-peak-kBps = <1132800>;
};
opp-1478400000 {
opp-hz = /bits/ 64 <1478400000>;
opp-supported-hw = <0x9>;
clock-latency-ns = <200000>;
opp-peak-kBps = <1190400>;
};
opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
opp-supported-hw = <0x04>;
clock-latency-ns = <200000>;
opp-peak-kBps = <1305600>;
};
opp-1593600000 {
opp-hz = /bits/ 64 <1593600000>;
opp-supported-hw = <0x9>;
clock-latency-ns = <200000>;
opp-peak-kBps = <1382400>;
};
};
@ -247,136 +270,163 @@
opp-hz = /bits/ 64 <307200000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <307200>;
};
opp-403200000 {
opp-hz = /bits/ 64 <403200000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <307200>;
};
opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <307200>;
};
opp-556800000 {
opp-hz = /bits/ 64 <556800000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <307200>;
};
opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <307200>;
};
opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <307200>;
};
opp-806400000 {
opp-hz = /bits/ 64 <806400000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <384000>;
};
opp-883200000 {
opp-hz = /bits/ 64 <883200000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <460800>;
};
opp-940800000 {
opp-hz = /bits/ 64 <940800000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <537600>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <595200>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <672000>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <672000>;
};
opp-1248000000 {
opp-hz = /bits/ 64 <1248000000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <748800>;
};
opp-1324800000 {
opp-hz = /bits/ 64 <1324800000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <825600>;
};
opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <902400>;
};
opp-1478400000 {
opp-hz = /bits/ 64 <1478400000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <979200>;
};
opp-1555200000 {
opp-hz = /bits/ 64 <1555200000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <1056000>;
};
opp-1632000000 {
opp-hz = /bits/ 64 <1632000000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <1190400>;
};
opp-1708800000 {
opp-hz = /bits/ 64 <1708800000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <1228800>;
};
opp-1785600000 {
opp-hz = /bits/ 64 <1785600000>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
opp-peak-kBps = <1305600>;
};
opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-supported-hw = <0xe>;
clock-latency-ns = <200000>;
opp-peak-kBps = <1305600>;
};
opp-1824000000 {
opp-hz = /bits/ 64 <1824000000>;
opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
opp-peak-kBps = <1382400>;
};
opp-1900800000 {
opp-hz = /bits/ 64 <1900800000>;
opp-supported-hw = <0x4>;
clock-latency-ns = <200000>;
opp-peak-kBps = <1305600>;
};
opp-1920000000 {
opp-hz = /bits/ 64 <1920000000>;
opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
opp-peak-kBps = <1459200>;
};
opp-1996800000 {
opp-hz = /bits/ 64 <1996800000>;
opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
opp-peak-kBps = <1593600>;
};
opp-2073600000 {
opp-hz = /bits/ 64 <2073600000>;
opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
opp-peak-kBps = <1593600>;
};
opp-2150400000 {
opp-hz = /bits/ 64 <2150400000>;
opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
opp-peak-kBps = <1593600>;
};
};
@ -398,6 +448,63 @@
method = "smc";
};
rpm: remoteproc {
compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc";
glink-edge {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8996";
qcom,glink-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
#clock-cells = <1>;
clocks = <&xo_board>;
clock-names = "xo";
};
rpmpd: power-controller {
compatible = "qcom,msm8996-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp1: opp1 {
opp-level = <1>;
};
rpmpd_opp2: opp2 {
opp-level = <2>;
};
rpmpd_opp3: opp3 {
opp-level = <3>;
};
rpmpd_opp4: opp4 {
opp-level = <4>;
};
rpmpd_opp5: opp5 {
opp-level = <5>;
};
rpmpd_opp6: opp6 {
opp-level = <6>;
};
};
};
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@ -472,62 +579,6 @@
};
};
rpm-glink {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8996";
qcom,glink-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
#clock-cells = <1>;
clocks = <&xo_board>;
clock-names = "xo";
};
rpmpd: power-controller {
compatible = "qcom,msm8996-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp1: opp1 {
opp-level = <1>;
};
rpmpd_opp2: opp2 {
opp-level = <2>;
};
rpmpd_opp3: opp3 {
opp-level = <3>;
};
rpmpd_opp4: opp4 {
opp-level = <4>;
};
rpmpd_opp5: opp5 {
opp-level = <5>;
};
rpmpd_opp6: opp6 {
opp-level = <6>;
};
};
};
};
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
@ -538,7 +589,7 @@
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 10>;
@ -1075,7 +1126,7 @@
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
interrupts = <5>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_BYTE1_CLK>,
@ -1136,11 +1187,11 @@
status = "disabled";
};
mdss_hdmi: mdss_hdmi-tx@9a0000 {
compatible = "qcom,mdss_hdmi-tx-8996";
reg = <0x009a0000 0x50c>,
<0x00070000 0x6158>,
<0x009e0000 0xfff>;
mdss_hdmi: hdmi-tx@9a0000 {
compatible = "qcom,hdmi-tx-8996";
reg = <0x009a0000 0x50c>,
<0x00070000 0x6158>,
<0x009e0000 0xfff>;
reg-names = "core_physical",
"qfprom_physical",
"hdcp_physical";
@ -1180,7 +1231,7 @@
mdss_hdmi_phy: phy@9a0600 {
#phy-cells = <0>;
compatible = "qcom,mdss_hdmi-phy-8996";
compatible = "qcom,hdmi-phy-8996";
reg = <0x009a0600 0x1c4>,
<0x009a0a00 0x124>,
<0x009a0c00 0x124>,
@ -1213,7 +1264,7 @@
reg = <0x00b00000 0x3f000>;
reg-names = "kgsl_3d0_reg_memory";
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mmcc GPU_GX_GFX3D_CLK>,
<&mmcc GPU_AHB_CLK>,
@ -3003,7 +3054,7 @@
usb3_dwc3: usb@6a00000 {
compatible = "snps,dwc3";
reg = <0x06a00000 0xcc00>;
interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hsusb_phy1>, <&ssusb_phy_0>;
phy-names = "usb2-phy", "usb3-phy";
snps,hird-threshold = /bits/ 8 <0>;
@ -3336,6 +3387,9 @@
#size-cells = <1>;
ranges;
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq";
clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
<&gcc GCC_USB20_MASTER_CLK>,
<&gcc GCC_USB20_MOCK_UTMI_CLK>,
@ -3358,7 +3412,7 @@
usb2_dwc3: usb@7600000 {
compatible = "snps,dwc3";
reg = <0x07600000 0xcc00>;
interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hsusb_phy2>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
@ -3372,7 +3426,7 @@
qcom,controlled-remotely;
reg = <0x09184000 0x32000>;
num-channels = <31>;
interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
qcom,ee = <1>;
qcom,num-ees = <2>;
@ -3381,7 +3435,7 @@
slim_msm: slim-ngd@91c0000 {
compatible = "qcom,slim-ngd-v1.5.0";
reg = <0x091c0000 0x2c000>;
interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&slimbam 3>, <&slimbam 4>;
dma-names = "rx", "tx";
#address-cells = <1>;
@ -3551,6 +3605,7 @@
reg = <0x09a11000 0x10000>;
clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
#clock-cells = <0>;
#interconnect-cells = <1>;
};
intc: interrupt-controller@9bc0000 {

2
arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts
View File

@ -106,7 +106,7 @@
&sound {
compatible = "qcom,apq8096-sndcard";
model = "natrium";
audio-routing = "RX_BIAS", "MCLK";
audio-routing = "RX_BIAS", "MCLK";
mm1-dai-link {
link-name = "MultiMedia1";

2
arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts
View File

@ -31,7 +31,7 @@
*/
extcon_usb: extcon-usb {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&tlmm 38 GPIO_ACTIVE_HIGH>;
id-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>;
};
gpio-hall-sensors {

1
arch/arm64/boot/dts/qcom/msm8998-mtp.dts
View File

@ -11,6 +11,7 @@
/ {
model = "Qualcomm Technologies, Inc. MSM8998 v1 MTP";
compatible = "qcom,msm8998-mtp", "qcom,msm8998";
chassis-type = "handset";
qcom,board-id = <8 0>;

4
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi
View File

@ -89,8 +89,8 @@
extcon_usb: extcon-usb {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&tlmm 38 GPIO_ACTIVE_HIGH>;
vbus-gpio = <&tlmm 128 GPIO_ACTIVE_HIGH>;
id-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>;
vbus-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cc_dir_default &usb_detect_en>;
};

1
arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts
View File

@ -213,7 +213,6 @@
rmi4-f1a@1a {
reg = <0x1a>;
syna,codes = <KEY_BACK KEY_APPSELECT>;
};
};
};

417
arch/arm64/boot/dts/qcom/msm8998.dtsi
View File

@ -316,73 +316,98 @@
};
};
dsi_opp_table: opp-table-dsi {
compatible = "operating-points-v2";
opp-131250000 {
opp-hz = /bits/ 64 <131250000>;
required-opps = <&rpmpd_opp_low_svs>;
};
opp-210000000 {
opp-hz = /bits/ 64 <210000000>;
required-opps = <&rpmpd_opp_svs>;
};
opp-312500000 {
opp-hz = /bits/ 64 <312500000>;
required-opps = <&rpmpd_opp_nom>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
rpm-glink {
compatible = "qcom,glink-rpm";
rpm: remoteproc {
compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
glink-edge {
compatible = "qcom,glink-rpm";
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8998";
qcom,glink-channels = "rpm_requests";
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
#clock-cells = <1>;
};
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8998";
qcom,glink-channels = "rpm_requests";
rpmpd: power-controller {
compatible = "qcom,msm8998-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
clocks = <&xo>;
clock-names = "xo";
#clock-cells = <1>;
};
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd: power-controller {
compatible = "qcom,msm8998-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_ret: opp1 {
opp-level = <RPM_SMD_LEVEL_RETENTION>;
};
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp_ret_plus: opp2 {
opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
};
rpmpd_opp_ret: opp1 {
opp-level = <RPM_SMD_LEVEL_RETENTION>;
};
rpmpd_opp_min_svs: opp3 {
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
};
rpmpd_opp_ret_plus: opp2 {
opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
};
rpmpd_opp_low_svs: opp4 {
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
};
rpmpd_opp_min_svs: opp3 {
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
};
rpmpd_opp_svs: opp5 {
opp-level = <RPM_SMD_LEVEL_SVS>;
};
rpmpd_opp_low_svs: opp4 {
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
};
rpmpd_opp_svs_plus: opp6 {
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
};
rpmpd_opp_svs: opp5 {
opp-level = <RPM_SMD_LEVEL_SVS>;
};
rpmpd_opp_nom: opp7 {
opp-level = <RPM_SMD_LEVEL_NOM>;
};
rpmpd_opp_svs_plus: opp6 {
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
};
rpmpd_opp_nom_plus: opp8 {
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
};
rpmpd_opp_nom: opp7 {
opp-level = <RPM_SMD_LEVEL_NOM>;
};
rpmpd_opp_turbo: opp9 {
opp-level = <RPM_SMD_LEVEL_TURBO>;
};
rpmpd_opp_nom_plus: opp8 {
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
};
rpmpd_opp_turbo_plus: opp10 {
opp-level = <RPM_SMD_LEVEL_BINNING>;
rpmpd_opp_turbo: opp9 {
opp-level = <RPM_SMD_LEVEL_TURBO>;
};
rpmpd_opp_turbo_plus: opp10 {
opp-level = <RPM_SMD_LEVEL_BINNING>;
};
};
};
};
@ -909,10 +934,10 @@
pcie0: pci@1c00000 {
compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
reg = <0x01c00000 0x2000>,
<0x1b000000 0xf1d>,
<0x1b000f20 0xa8>,
<0x1b100000 0x100000>;
reg = <0x01c00000 0x2000>,
<0x1b000000 0xf1d>,
<0x1b000f20 0xa8>,
<0x1b100000 0x100000>;
reg-names = "parf", "dbi", "elbi", "config";
device_type = "pci";
linux,pci-domain = <0>;
@ -1488,7 +1513,7 @@
"rbcpr",
"core";
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&adreno_smmu 0>;
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&rpmpd MSM8998_VDDMX>;
@ -1574,7 +1599,7 @@
reg = <0x05065000 0x9000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GPLL0_OUT_MAIN>;
<&gcc GCC_GPU_GPLL0_CLK>;
clock-names = "xo",
"gpll0";
};
@ -2074,11 +2099,11 @@
spmi_bus: spmi@800f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0800f000 0x1000>,
<0x08400000 0x1000000>,
<0x09400000 0x1000000>,
<0x0a400000 0x220000>,
<0x0800a000 0x3000>;
reg = <0x0800f000 0x1000>,
<0x08400000 0x1000000>,
<0x09400000 0x1000000>,
<0x0a400000 0x220000>,
<0x0800a000 0x3000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
@ -2718,16 +2743,274 @@
"dsi1byte",
"hdmipll",
"dplink",
"dpvco";
"dpvco",
"gpll0_div";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_MMSS_GPLL0_CLK>,
<&mdss_dsi0_phy 1>,
<&mdss_dsi0_phy 0>,
<&mdss_dsi1_phy 1>,
<&mdss_dsi1_phy 0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>;
<&gcc GCC_MMSS_GPLL0_DIV_CLK>;
};
mdss: display-subsystem@c900000 {
compatible = "qcom,msm8998-mdss";
reg = <0x0c900000 0x1000>;
reg-names = "mdss";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
clocks = <&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
<&mmcc MDSS_MDP_CLK>;
clock-names = "iface",
"bus",
"core";
power-domains = <&mmcc MDSS_GDSC>;
iommus = <&mmss_smmu 0>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
mdss_mdp: display-controller@c901000 {
compatible = "qcom,msm8998-dpu";
reg = <0x0c901000 0x8f000>,
<0x0c9a8e00 0xf0>,
<0x0c9b0000 0x2008>,
<0x0c9b8000 0x1040>;
reg-names = "mdp",
"regdma",
"vbif",
"vbif_nrt";
interrupt-parent = <&mdss>;
interrupts = <0>;
clocks = <&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
<&mmcc MNOC_AHB_CLK>,
<&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_VSYNC_CLK>;
clock-names = "iface",
"bus",
"mnoc",
"core",
"vsync";
assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmpd MSM8998_VDDMX>;
mdp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-171430000 {
opp-hz = /bits/ 64 <171430000>;
required-opps = <&rpmpd_opp_low_svs>;
};
opp-275000000 {
opp-hz = /bits/ 64 <275000000>;
required-opps = <&rpmpd_opp_svs>;
};
opp-330000000 {
opp-hz = /bits/ 64 <330000000>;
required-opps = <&rpmpd_opp_nom>;
};
opp-412500000 {
opp-hz = /bits/ 64 <412500000>;
required-opps = <&rpmpd_opp_turbo>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&mdss_dsi0_in>;
};
};
port@1 {
reg = <1>;
dpu_intf2_out: endpoint {
remote-endpoint = <&mdss_dsi1_in>;
};
};
};
};
mdss_dsi0: dsi@c994000 {
compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x0c994000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
clocks = <&mmcc MDSS_BYTE0_CLK>,
<&mmcc MDSS_BYTE0_INTF_CLK>,
<&mmcc MDSS_PCLK0_CLK>,
<&mmcc MDSS_ESC0_CLK>,
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
<&mmcc PCLK0_CLK_SRC>;
assigned-clock-parents = <&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmpd MSM8998_VDDCX>;
phys = <&mdss_dsi0_phy>;
phy-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
mdss_dsi0_out: endpoint {
};
};
};
};
mdss_dsi0_phy: phy@c994400 {
compatible = "qcom,dsi-phy-10nm-8998";
reg = <0x0c994400 0x200>,
<0x0c994600 0x280>,
<0x0c994a00 0x1e0>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
clocks = <&mmcc MDSS_AHB_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "ref";
#clock-cells = <1>;
#phy-cells = <0>;
status = "disabled";
};
mdss_dsi1: dsi@c996000 {
compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x0c996000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <5>;
clocks = <&mmcc MDSS_BYTE1_CLK>,
<&mmcc MDSS_BYTE1_INTF_CLK>,
<&mmcc MDSS_PCLK1_CLK>,
<&mmcc MDSS_ESC1_CLK>,
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
<&mmcc PCLK1_CLK_SRC>;
assigned-clock-parents = <&mdss_dsi1_phy 0>,
<&mdss_dsi1_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmpd MSM8998_VDDCX>;
phys = <&mdss_dsi1_phy>;
phy-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dsi1_in: endpoint {
remote-endpoint = <&dpu_intf2_out>;
};
};
port@1 {
reg = <1>;
mdss_dsi1_out: endpoint {
};
};
};
};
mdss_dsi1_phy: phy@c996400 {
compatible = "qcom,dsi-phy-10nm-8998";
reg = <0x0c996400 0x200>,
<0x0c996600 0x280>,
<0x0c996a00 0x10e>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
clocks = <&mmcc MDSS_AHB_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface",
"ref";
#clock-cells = <1>;
#phy-cells = <0>;
status = "disabled";
};
};
mmss_smmu: iommu@cd00000 {
@ -2737,10 +3020,10 @@
clocks = <&mmcc MNOC_AHB_CLK>,
<&mmcc BIMC_SMMU_AHB_CLK>,
<&rpmcc RPM_SMD_MMAXI_CLK>,
<&mmcc BIMC_SMMU_AXI_CLK>;
clock-names = "iface-mm", "iface-smmu",
"bus-mm", "bus-smmu";
clock-names = "iface-mm",
"iface-smmu",
"bus-smmu";
#global-interrupts = <0>;
interrupts =
@ -2764,6 +3047,8 @@
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc BIMC_SMMU_GDSC>;
};
remoteproc_adsp: remoteproc@17300000 {

18
arch/arm64/boot/dts/qcom/pm6125.dtsi
View File

@ -85,36 +85,42 @@
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
#io-channel-cells = <1>;
ref-gnd@0 {
channel@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
label = "ref_gnd";
};
vref-1p25@1 {
channel@1 {
reg = <ADC5_1P25VREF>;
qcom,pre-scaling = <1 1>;
label = "vref_1p25";
};
die-temp@6 {
channel@6 {
reg = <ADC5_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "die_temp";
};
vph-pwr@83 {
channel@83 {
reg = <ADC5_VPH_PWR>;
qcom,pre-scaling = <1 3>;
label = "vph_pwr";
};
vcoin@85 {
channel@85 {
reg = <ADC5_VCOIN>;
qcom,pre-scaling = <1 3>;
label = "vcoin";
};
xo-therm@4c {
channel@4c {
reg = <ADC5_XO_THERM_100K_PU>;
qcom,pre-scaling = <1 1>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "xo_therm";
};
};

2
arch/arm64/boot/dts/qcom/pm6150.dtsi
View File

@ -72,7 +72,7 @@
#size-cells = <0>;
#io-channel-cells = <1>;
adc-chan@6 {
channel@6 {
reg = <ADC5_DIE_TEMP>;
label = "die_temp";
};

13
arch/arm64/boot/dts/qcom/pm6150l.dtsi
View File

@ -60,25 +60,25 @@
#size-cells = <0>;
#io-channel-cells = <1>;
adc-chan@0 {
channel@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
label = "ref_gnd";
};
adc-chan@1 {
channel@1 {
reg = <ADC5_1P25VREF>;
qcom,pre-scaling = <1 1>;
label = "vref_1p25";
};
adc-chan@6 {
channel@6 {
reg = <ADC5_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "die_temp";
};
adc-chan@83 {
channel@83 {
reg = <ADC5_VPH_PWR>;
qcom,pre-scaling = <1 3>;
label = "vph_pwr";
@ -121,8 +121,9 @@
pm6150l_wled: leds@d800 {
compatible = "qcom,pm6150l-wled";
reg = <0xd800>, <0xd900>;
interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp";
interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
<0x5 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp", "short";
label = "backlight";
status = "disabled";

33
arch/arm64/boot/dts/qcom/pm660.dtsi
View File

@ -91,82 +91,93 @@
#size-cells = <0>;
#io-channel-cells = <1>;
ref_gnd: ref_gnd@0 {
channel@0 {
reg = <ADC5_REF_GND>;
qcom,decimation = <1024>;
qcom,pre-scaling = <1 1>;
label = "ref_gnd";
};
vref_1p25: vref_1p25@1 {
channel@1 {
reg = <ADC5_1P25VREF>;
qcom,decimation = <1024>;
qcom,pre-scaling = <1 1>;
label = "vref_1p25";
};
die_temp: die_temp@6 {
channel@6 {
reg = <ADC5_DIE_TEMP>;
qcom,decimation = <1024>;
qcom,pre-scaling = <1 1>;
label = "die_temp";
};
xo_therm: xo_therm@4c {
channel@4c {
reg = <ADC5_XO_THERM_100K_PU>;
qcom,pre-scaling = <1 1>;
qcom,decimation = <1024>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "xo_therm";
};
msm_therm: msm_therm@4d {
channel@4d {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,pre-scaling = <1 1>;
qcom,decimation = <1024>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "msm_therm";
};
emmc_therm: emmc_therm@4e {
channel@4e {
reg = <ADC5_AMUX_THM2_100K_PU>;
qcom,pre-scaling = <1 1>;
qcom,decimation = <1024>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "emmc_therm";
};
pa_therm0: thermistor0@4f {
channel@4f {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,pre-scaling = <1 1>;
qcom,decimation = <1024>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "pa_therm0";
};
pa_therm1: thermistor1@50 {
channel@50 {
reg = <ADC5_AMUX_THM4_100K_PU>;
qcom,pre-scaling = <1 1>;
qcom,decimation = <1024>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "pa_therm1";
};
quiet_therm: quiet_therm@51 {
channel@51 {
reg = <ADC5_AMUX_THM5_100K_PU>;
qcom,pre-scaling = <1 1>;
qcom,decimation = <1024>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "quiet_therm";
};
vadc_vph_pwr: vph_pwr@83 {
channel@83 {
reg = <ADC5_VPH_PWR>;
qcom,decimation = <1024>;
qcom,pre-scaling = <1 3>;
label = "vph_pwr";
};
vcoin: vcoin@85 {
channel@85 {
reg = <ADC5_VCOIN>;
qcom,decimation = <1024>;
qcom,pre-scaling = <1 3>;
label = "vcoin";
};
};

5
arch/arm64/boot/dts/qcom/pm660l.dtsi
View File

@ -74,8 +74,9 @@
pm660l_wled: leds@d800 {
compatible = "qcom,pm660l-wled";
reg = <0xd800>, <0xd900>;
interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp";
interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
<0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp", "short";
label = "backlight";
status = "disabled";

34
arch/arm64/boot/dts/qcom/pm7250b.dtsi
View File

@ -62,56 +62,56 @@
#io-channel-cells = <1>;
interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
adc-chan@0 {
channel@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
label = "ref_gnd";
};
adc-chan@1 {
channel@1 {
reg = <ADC5_1P25VREF>;
qcom,pre-scaling = <1 1>;
label = "vref_1p25";
};
adc-chan@2 {
channel@2 {
reg = <ADC5_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "die_temp";
};
adc-chan@7 {
channel@7 {
reg = <ADC5_USB_IN_I>;
qcom,pre-scaling = <1 1>;
label = "usb_in_i_uv";
};
adc-chan@8 {
channel@8 {
reg = <ADC5_USB_IN_V_16>;
qcom,pre-scaling = <1 16>;
label = "usb_in_v_div_16";
};
adc-chan@9 {
channel@9 {
reg = <ADC5_CHG_TEMP>;
qcom,pre-scaling = <1 1>;
label = "chg_temp";
};
adc-chan@e {
channel@e {
reg = <ADC5_AMUX_THM2>;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "smb1390_therm";
};
adc-chan@1e {
channel@1e {
reg = <ADC5_MID_CHG_DIV6>;
qcom,pre-scaling = <1 6>;
label = "chg_mid";
};
adc-chan@4b {
channel@4b {
reg = <ADC5_BAT_ID_100K_PU>;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
@ -119,19 +119,19 @@
label = "bat_id";
};
adc-chan@83 {
channel@83 {
reg = <ADC5_VPH_PWR>;
qcom,pre-scaling = <1 3>;
label = "vph_pwr";
};
adc-chan@84 {
channel@84 {
reg = <ADC5_VBAT_SNS>;
qcom,pre-scaling = <1 3>;
label = "vbat_sns";
};
adc-chan@99 {
channel@99 {
reg = <ADC5_SBUx>;
qcom,pre-scaling = <1 3>;
label = "chg_sbux";
@ -147,6 +147,16 @@
#size-cells = <0>;
status = "disabled";
};
pm7250b_gpios: pinctrl@c000 {
compatible = "qcom,pm7250b-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pm7250b_gpios 0 0 12>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pmic@3 {

70
arch/arm64/boot/dts/qcom/pm7550ba.dtsi Normal file
View File

@ -0,0 +1,70 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pm7550ba-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm7550ba_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pm7550ba: pmic@7 {
compatible = "qcom,pm7550ba", "qcom,spmi-pmic";
reg = <7 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm7550ba_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm7550ba_gpios: gpio@8800 {
compatible = "qcom,pm7550ba-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pm7550ba_gpios 0 0 8>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pm7550ba_eusb2_repeater: phy@fd00 {
compatible = "qcom,pm7550ba-eusb2-repeater", "qcom,pm8550b-eusb2-repeater";
reg = <0xfd00>;
#phy-cells = <0>;
};
};
};

6
arch/arm64/boot/dts/qcom/pm8150.dtsi
View File

@ -90,19 +90,19 @@
#io-channel-cells = <1>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
ref-gnd@0 {
channel@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
label = "ref_gnd";
};
vref-1p25@1 {
channel@1 {
reg = <ADC5_1P25VREF>;
qcom,pre-scaling = <1 1>;
label = "vref_1p25";
};
die-temp@6 {
channel@6 {
reg = <ADC5_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "die_temp";

8
arch/arm64/boot/dts/qcom/pm8150b.dtsi
View File

@ -76,25 +76,25 @@
#io-channel-cells = <1>;
interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
ref-gnd@0 {
channel@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
label = "ref_gnd";
};
vref-1p25@1 {
channel@1 {
reg = <ADC5_1P25VREF>;
qcom,pre-scaling = <1 1>;
label = "vref_1p25";
};
die-temp@6 {
channel@6 {
reg = <ADC5_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "die_temp";
};
chg-temp@9 {
channel@9 {
reg = <ADC5_CHG_TEMP>;
qcom,pre-scaling = <1 1>;
label = "chg_temp";

6
arch/arm64/boot/dts/qcom/pm8150l.dtsi
View File

@ -70,19 +70,19 @@
#io-channel-cells = <1>;
interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
ref-gnd@0 {
channel@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
label = "ref_gnd";
};
vref-1p25@1 {
channel@1 {
reg = <ADC5_1P25VREF>;
qcom,pre-scaling = <1 1>;
label = "vref_1p25";
};
die-temp@6 {
channel@6 {
reg = <ADC5_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "die_temp";

2
arch/arm64/boot/dts/qcom/pm8350.dtsi
View File

@ -8,7 +8,7 @@
/ {
thermal-zones {
pm8350_thermal: pm8350c-thermal {
pm8350_thermal: pm8350-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm8350_temp_alarm>;

2
arch/arm64/boot/dts/qcom/pm8350b.dtsi
View File

@ -8,7 +8,7 @@
/ {
thermal-zones {
pm8350b_thermal: pm8350c-thermal {
pm8350b_thermal: pm8350b-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm8350b_temp_alarm>;

14
arch/arm64/boot/dts/qcom/pm8916.dtsi
View File

@ -66,27 +66,27 @@
#size-cells = <0>;
#io-channel-cells = <1>;
adc-chan@0 {
channel@0 {
reg = <VADC_USBIN>;
qcom,pre-scaling = <1 10>;
};
adc-chan@7 {
channel@7 {
reg = <VADC_VSYS>;
qcom,pre-scaling = <1 3>;
};
adc-chan@8 {
channel@8 {
reg = <VADC_DIE_TEMP>;
};
adc-chan@9 {
channel@9 {
reg = <VADC_REF_625MV>;
};
adc-chan@a {
channel@a {
reg = <VADC_REF_1250MV>;
};
adc-chan@e {
channel@e {
reg = <VADC_GND_REF>;
};
adc-chan@f {
channel@f {
reg = <VADC_VDD_VADC>;
};
};

39
arch/arm64/boot/dts/qcom/pm8950.dtsi
View File

@ -50,77 +50,90 @@
#size-cells = <0>;
#io-channel-cells = <1>;
vcoin@5 {
channel@5 {
reg = <VADC_VCOIN>;
qcom,pre-scaling = <1 1>;
label = "vcoin";
};
vph-pwr@7 {
channel@7 {
reg = <VADC_VSYS>;
qcom,pre-scaling = <1 1>;
label = "vph_pwr";
};
die-temp@8 {
channel@8 {
reg = <VADC_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "die_temp";
};
ref-625mv@9 {
channel@9 {
reg = <VADC_REF_625MV>;
qcom,pre-scaling = <1 1>;
label = "ref_625mv";
};
ref-1250mv@a {
channel@a {
reg = <VADC_REF_1250MV>;
qcom,pre-scaling = <1 1>;
label = "ref_1250mv";
};
ref-buf-625mv@c {
channel@c {
reg = <VADC_SPARE1>;
qcom,pre-scaling = <1 1>;
label = "ref_buf_625mv";
};
ref-gnd@e {
channel@e {
reg = <VADC_GND_REF>;
label = "ref_gnd";
};
ref-vdd@f {
channel@f {
reg = <VADC_VDD_VADC>;
label = "ref_vdd";
};
pa-therm1@11 {
channel@11 {
reg = <VADC_P_MUX2_1_1>;
qcom,pre-scaling = <1 1>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
label = "pa_therm1";
};
case-therm@13 {
channel@13 {
reg = <VADC_P_MUX4_1_1>;
qcom,pre-scaling = <1 1>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
label = "case_therm";
};
xo-therm@32 {
channel@32 {
reg = <VADC_LR_MUX3_XO_THERM>;
qcom,pre-scaling = <1 1>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
label = "xo_therm";
};
pa-therm0@36 {
channel@36 {
reg = <VADC_LR_MUX7_HW_ID>;
qcom,pre-scaling = <1 1>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
label = "pa_therm0";
};
xo-therm-buf@3c {
channel@3c {
reg = <VADC_LR_MUX3_BUF_XO_THERM>;
qcom,pre-scaling = <1 1>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
label = "xo_therm_buf";
};
};

45
arch/arm64/boot/dts/qcom/pm8953.dtsi
View File

@ -6,6 +6,37 @@
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pm8953-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm8953_temp>;
trips {
trip0 {
temperature = <105000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <125000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pmic@0 {
compatible = "qcom,pm8953", "qcom,spmi-pmic";
@ -36,7 +67,7 @@
};
};
temp-alarm@2400 {
pm8953_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
@ -53,22 +84,22 @@
#size-cells = <0>;
#io-channel-cells = <1>;
adc-chan@8 {
channel@8 {
reg = <VADC_DIE_TEMP>;
};
adc-chan@9 {
channel@9 {
reg = <VADC_REF_625MV>;
};
adc-chan@a {
channel@a {
reg = <VADC_REF_1250MV>;
};
adc-chan@c {
channel@c {
reg = <VADC_SPARE1>;
};
adc-chan@e {
channel@e {
reg = <VADC_GND_REF>;
};
adc-chan@f {
channel@f {
reg = <VADC_VDD_VADC>;
};
};

12
arch/arm64/boot/dts/qcom/pm8994.dtsi
View File

@ -83,27 +83,27 @@
#size-cells = <0>;
#io-channel-cells = <1>;
adc-chan@7 {
channel@7 {
reg = <VADC_VSYS>;
qcom,pre-scaling = <1 3>;
label = "vph_pwr";
};
adc-chan@8 {
channel@8 {
reg = <VADC_DIE_TEMP>;
label = "die_temp";
};
adc-chan@9 {
channel@9 {
reg = <VADC_REF_625MV>;
label = "ref_625mv";
};
adc-chan@a {
channel@a {
reg = <VADC_REF_1250MV>;
label = "ref_1250mv";
};
adc-chan@e {
channel@e {
reg = <VADC_GND_REF>;
};
adc-chan@f {
channel@f {
reg = <VADC_VDD_VADC>;
};
};

2
arch/arm64/boot/dts/qcom/pm8998.dtsi
View File

@ -86,7 +86,7 @@
#size-cells = <0>;
#io-channel-cells = <1>;
adc-chan@6 {
channel@6 {
reg = <ADC5_DIE_TEMP>;
label = "die_temp";
};

17
arch/arm64/boot/dts/qcom/pmi8950.dtsi
View File

@ -20,37 +20,37 @@
#size-cells = <0>;
#io-channel-cells = <1>;
adc-chan@0 {
channel@0 {
reg = <VADC_USBIN>;
qcom,pre-scaling = <1 4>;
label = "usbin";
};
adc-chan@1 {
channel@1 {
reg = <VADC_DCIN>;
qcom,pre-scaling = <1 4>;
label = "dcin";
};
adc-chan@2 {
channel@2 {
reg = <VADC_VCHG_SNS>;
qcom,pre-scaling = <1 1>;
label = "vchg_sns";
};
adc-chan@9 {
channel@9 {
reg = <VADC_REF_625MV>;
qcom,pre-scaling = <1 1>;
label = "ref_625mv";
};
adc-chan@a {
channel@a {
reg = <VADC_REF_1250MV>;
qcom,pre-scaling = <1 1>;
label = "ref_1250mv";
};
adc-chan@d {
channel@d {
reg = <VADC_SPARE2>;
qcom,pre-scaling = <1 1>;
label = "chg_temp";
@ -87,8 +87,9 @@
pmi8950_wled: leds@d800 {
compatible = "qcom,pmi8950-wled";
reg = <0xd800>, <0xd900>;
interrupts = <0x3 0xd8 0x02 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "short";
interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
<0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp", "short";
label = "backlight";
status = "disabled";

5
arch/arm64/boot/dts/qcom/pmi8994.dtsi
View File

@ -54,8 +54,9 @@
pmi8994_wled: wled@d800 {
compatible = "qcom,pmi8994-wled";
reg = <0xd800>, <0xd900>;
interrupts = <3 0xd8 0x02 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "short";
interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
<0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp", "short";
qcom,cabc;
qcom,external-pfet;
status = "disabled";

2
arch/arm64/boot/dts/qcom/pmk8350.dtsi
View File

@ -59,7 +59,7 @@
};
pmk8350_adc_tm: adc-tm@3400 {
compatible = "qcom,adc-tm7";
compatible = "qcom,spmi-adc-tm5-gen2";
reg = <0x3400>;
interrupts = <PMK8350_SID 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;

6
arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi
View File

@ -77,19 +77,19 @@
#io-channel-cells = <1>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
ref-gnd@0 {
channel@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
label = "ref_gnd";
};
vref-1p25@1 {
channel@1 {
reg = <ADC5_1P25VREF>;
qcom,pre-scaling = <1 1>;
label = "vref_1p25";
};
die-temp@6 {
channel@6 {
reg = <ADC5_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "die_temp";

6
arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi
View File

@ -69,19 +69,19 @@
#io-channel-cells = <1>;
interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
ref-gnd@0 {
channel@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
label = "ref_gnd";
};
vref-1p25@1 {
channel@1 {
reg = <ADC5_1P25VREF>;
qcom,pre-scaling = <1 1>;
label = "vref_1p25";
};
die-temp@6 {
channel@6 {
reg = <ADC5_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "die_temp";

27
arch/arm64/boot/dts/qcom/pmp8074.dtsi
View File

@ -18,57 +18,66 @@
#size-cells = <0>;
#io-channel-cells = <1>;
ref-gnd@0 {
channel@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
label = "ref_gnd";
};
vref-1p25@1 {
channel@1 {
reg = <ADC5_1P25VREF>;
qcom,pre-scaling = <1 1>;
label = "vref_1p25";
};
vref-vadc@2 {
channel@2 {
reg = <ADC5_VREF_VADC>;
qcom,pre-scaling = <1 1>;
label = "vref_vadc";
};
pmic_die: die-temp@6 {
channel@6 {
reg = <ADC5_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "pmic_die";
};
xo_therm: xo-temp@76 {
channel@76 {
reg = <ADC5_XO_THERM_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "xo_therm";
};
pa_therm1: thermistor1@77 {
channel@77 {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "pa_therm1";
};
pa_therm2: thermistor2@78 {
channel@78 {
reg = <ADC5_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "pa_therm2";
};
pa_therm3: thermistor3@79 {
channel@79 {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "pa_therm3";
};
vph-pwr@131 {
channel@131 {
reg = <ADC5_VPH_PWR>;
qcom,pre-scaling = <1 3>;
label = "vph_pwr";
};
};

2
arch/arm64/boot/dts/qcom/pmr735b.dtsi
View File

@ -8,7 +8,7 @@
/ {
thermal-zones {
pmr735a_thermal: pmr735a-thermal {
pmr735b_thermal: pmr735b-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmr735b_temp_alarm>;

21
arch/arm64/boot/dts/qcom/pms405.dtsi
View File

@ -81,45 +81,52 @@
#size-cells = <0>;
#io-channel-cells = <1>;
ref_gnd@0 {
channel@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
label = "ref_gnd";
};
vref_1p25@1 {
channel@1 {
reg = <ADC5_1P25VREF>;
qcom,pre-scaling = <1 1>;
label = "vref_1p25";
};
pon_1: vph_pwr@131 {
channel@131 {
reg = <ADC5_VPH_PWR>;
qcom,pre-scaling = <1 3>;
label = "vph_pwr";
};
die_temp@6 {
channel@6 {
reg = <ADC5_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "die_temp";
};
pa_therm1: thermistor1@77 {
channel@77 {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "pa_therm1";
};
pa_therm3: thermistor3@79 {
channel@79 {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "pa_therm3";
};
xo_therm: xo_temp@76 {
channel@76 {
reg = <ADC5_XO_THERM_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "xo_therm";
};
};

64
arch/arm64/boot/dts/qcom/pmx75.dtsi Normal file
View File

@ -0,0 +1,64 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pmx75-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmx75_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pmx75: pmic@1 {
compatible = "qcom,pmx75", "qcom,spmi-pmic";
reg = <1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmx75_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmx75_gpios: gpio@8800 {
compatible = "qcom,pmx75-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmx75_gpios 0 0 16>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

158
arch/arm64/boot/dts/qcom/qcm2290.dtsi
View File

@ -198,6 +198,71 @@
};
};
rpm: remoteproc {
compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc";
glink-edge {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-qcm2290";
qcom,glink-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc";
clocks = <&xo_board>;
clock-names = "xo";
#clock-cells = <1>;
};
rpmpd: power-controller {
compatible = "qcom,qcm2290-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp_min_svs: opp1 {
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
};
rpmpd_opp_low_svs: opp2 {
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
};
rpmpd_opp_svs: opp3 {
opp-level = <RPM_SMD_LEVEL_SVS>;
};
rpmpd_opp_svs_plus: opp4 {
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
};
rpmpd_opp_nom: opp5 {
opp-level = <RPM_SMD_LEVEL_NOM>;
};
rpmpd_opp_nom_plus: opp6 {
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
};
rpmpd_opp_turbo: opp7 {
opp-level = <RPM_SMD_LEVEL_TURBO>;
};
rpmpd_opp_turbo_plus: opp8 {
opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
};
};
};
};
};
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@ -288,67 +353,6 @@
};
};
rpm-glink {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-qcm2290";
qcom,glink-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc";
clocks = <&xo_board>;
clock-names = "xo";
#clock-cells = <1>;
};
rpmpd: power-controller {
compatible = "qcom,qcm2290-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp_min_svs: opp1 {
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
};
rpmpd_opp_low_svs: opp2 {
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
};
rpmpd_opp_svs: opp3 {
opp-level = <RPM_SMD_LEVEL_SVS>;
};
rpmpd_opp_svs_plus: opp4 {
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
};
rpmpd_opp_nom: opp5 {
opp-level = <RPM_SMD_LEVEL_NOM>;
};
rpmpd_opp_nom_plus: opp6 {
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
};
rpmpd_opp_turbo: opp7 {
opp-level = <RPM_SMD_LEVEL_TURBO>;
};
rpmpd_opp_turbo_plus: opp8 {
opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
};
};
};
};
};
smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
@ -638,6 +642,32 @@
status = "disabled";
};
usb_qmpphy: phy@1615000 {
compatible = "qcom,qcm2290-qmp-usb3-phy";
reg = <0x0 0x01615000 0x0 0x1000>;
clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "cfg_ahb",
"ref",
"com_aux",
"pipe";
resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
<&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
reset-names = "phy",
"phy_phy";
#clock-cells = <0>;
clock-output-names = "usb3_phy_pipe_clk_src";
#phy-cells = <0>;
status = "disabled";
};
qfprom@1b44000 {
compatible = "qcom,qcm2290-qfprom", "qcom,qfprom";
reg = <0x0 0x01b44000 0x0 0x3000>;
@ -790,7 +820,7 @@
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <10>;
dma-channels = <10>;
dma-channel-mask = <0x1f>;
iommus = <&apps_smmu 0xf6 0x0>;
#dma-cells = <3>;
@ -1062,8 +1092,8 @@
compatible = "snps,dwc3";
reg = <0x0 0x04e00000 0x0 0xcd00>;
interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb_hsphy>;
phy-names = "usb2-phy";
phys = <&usb_hsphy>, <&usb_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
iommus = <&apps_smmu 0x120 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;

160
arch/arm64/boot/dts/qcom/qcs404.dtsi
View File

@ -166,6 +166,84 @@
method = "smc";
};
rpm: remoteproc {
compatible = "qcom,qcs404-rpm-proc", "qcom,rpm-proc";
glink-edge {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-qcs404";
qcom,glink-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc";
#clock-cells = <1>;
clocks = <&xo_board>;
clock-names = "xo";
};
rpmpd: power-controller {
compatible = "qcom,qcs404-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp_ret: opp1 {
opp-level = <16>;
};
rpmpd_opp_ret_plus: opp2 {
opp-level = <32>;
};
rpmpd_opp_min_svs: opp3 {
opp-level = <48>;
};
rpmpd_opp_low_svs: opp4 {
opp-level = <64>;
};
rpmpd_opp_svs: opp5 {
opp-level = <128>;
};
rpmpd_opp_svs_plus: opp6 {
opp-level = <192>;
};
rpmpd_opp_nom: opp7 {
opp-level = <256>;
};
rpmpd_opp_nom_plus: opp8 {
opp-level = <320>;
};
rpmpd_opp_turbo: opp9 {
opp-level = <384>;
};
rpmpd_opp_turbo_no_cpr: opp10 {
opp-level = <416>;
};
rpmpd_opp_turbo_plus: opp11 {
opp-level = <512>;
};
};
};
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@ -217,80 +295,6 @@
};
};
rpm-glink {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-qcs404";
qcom,glink-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc";
#clock-cells = <1>;
clocks = <&xo_board>;
clock-names = "xo";
};
rpmpd: power-controller {
compatible = "qcom,qcs404-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp_ret: opp1 {
opp-level = <16>;
};
rpmpd_opp_ret_plus: opp2 {
opp-level = <32>;
};
rpmpd_opp_min_svs: opp3 {
opp-level = <48>;
};
rpmpd_opp_low_svs: opp4 {
opp-level = <64>;
};
rpmpd_opp_svs: opp5 {
opp-level = <128>;
};
rpmpd_opp_svs_plus: opp6 {
opp-level = <192>;
};
rpmpd_opp_nom: opp7 {
opp-level = <256>;
};
rpmpd_opp_nom_plus: opp8 {
opp-level = <320>;
};
rpmpd_opp_turbo: opp9 {
opp-level = <384>;
};
rpmpd_opp_turbo_no_cpr: opp10 {
opp-level = <416>;
};
rpmpd_opp_turbo_plus: opp11 {
opp-level = <512>;
};
};
};
};
};
smem {
compatible = "qcom,smem";
@ -1459,10 +1463,10 @@
pcie: pci@10000000 {
compatible = "qcom,pcie-qcs404";
reg = <0x10000000 0xf1d>,
<0x10000f20 0xa8>,
<0x07780000 0x2000>,
<0x10001000 0x2000>;
reg = <0x10000000 0xf1d>,
<0x10000f20 0xa8>,
<0x07780000 0x2000>,
<0x10001000 0x2000>;
reg-names = "dbi", "elbi", "parf", "config";
device_type = "pci";
linux,pci-domain = <0>;

26
arch/arm64/boot/dts/qcom/qdu1000-idp.dts
View File

@ -448,6 +448,28 @@
status = "okay";
};
&reserved_memory {
ecc_meta_data_mem: ecc-meta-data@e0000000 {
reg = <0x0 0xe0000000 0x0 0x20000000>;
no-map;
};
harq_buffer_mem: harq-buffer@800000000 {
reg = <0x8 0x0 0x0 0x80000000>;
no-map;
};
tenx_sp_buffer_mem: tenx-sp-buffer@880000000 {
reg = <0x8 0x80000000 0x0 0x50000000>;
no-map;
};
fapi_buffer_mem: fapi-buffer@8d0000000 {
reg = <0x8 0xd0000000 0x0 0x20000000>;
no-map;
};
};
&sdhc {
pinctrl-0 = <&sdc_on_state>;
pinctrl-1 = <&sdc_off_state>;
@ -471,6 +493,10 @@
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <28 2>;
};
&uart7 {
status = "okay";
};

266
arch/arm64/boot/dts/qcom/qrb2210-rb1.dts
View File

@ -38,6 +38,91 @@
wakeup-source;
};
};
vreg_hdmi_out_1p2: regulator-hdmi-out-1p2 {
compatible = "regulator-fixed";
regulator-name = "VREG_HDMI_OUT_1P2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
vin-supply = <&vdc_1v2>;
regulator-always-on;
regulator-boot-on;
};
lt9611_3v3: regulator-lt9611-3v3 {
compatible = "regulator-fixed";
regulator-name = "LT9611_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vdc_3v3>;
regulator-always-on;
regulator-boot-on;
};
/* Main barrel jack input */
vdc_12v: regulator-vdc-12v {
compatible = "regulator-fixed";
regulator-name = "DC_12V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
/* 1.2V supply stepped down from the barrel jack input */
vdc_1v2: regulator-vdc-1v2 {
compatible = "regulator-fixed";
regulator-name = "VDC_1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
vin-supply = <&vdc_12v>;
regulator-always-on;
regulator-boot-on;
};
/* 3.3V supply stepped down from the barrel jack input */
vdc_3v3: regulator-vdc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vdc_12v>;
regulator-always-on;
regulator-boot-on;
};
/* 5V supply stepped down from the barrel jack input */
vdc_5v: regulator-vdc-5v {
compatible = "regulator-fixed";
regulator-name = "VDC_5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
/* "Battery" voltage for the SoM, stepped down from the barrel jack input */
vdc_vbat_som: regulator-vdc-vbat {
compatible = "regulator-fixed";
regulator-name = "VBAT_SOM";
regulator-min-microvolt = <4200000>;
regulator-max-microvolt = <4200000>;
regulator-always-on;
regulator-boot-on;
};
/* PM2250 charger out, supplied by VBAT */
vph_pwr: regulator-vph-pwr {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
vin-supply = <&vdc_vbat_som>;
regulator-always-on;
regulator-boot-on;
};
};
&pm2250_resin {
@ -49,7 +134,183 @@
status = "okay";
};
&rpm_requests {
regulators {
compatible = "qcom,rpm-pm2250-regulators";
vdd_s3-supply = <&vph_pwr>;
vdd_s4-supply = <&vph_pwr>;
vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12-supply = <&pm2250_s3>;
vdd_l4_l17_l18_l19_l20_l21_l22-supply = <&vph_pwr>;
vdd_l13_l14_l15_l16-supply = <&pm2250_s4>;
/*
* S1 - VDD_APC
* S2 - VDD_CX
*/
pm2250_s3: s3 {
/* 0.4V-1.6625V -> 1.3V (Power tree requirements) */
regulator-min-microvolts = <1350000>;
regulator-max-microvolts = <1350000>;
regulator-boot-on;
};
pm2250_s4: s4 {
/* 1.2V-2.35V -> 2.05V (Power tree requirements) */
regulator-min-microvolts = <2072000>;
regulator-max-microvolts = <2072000>;
regulator-boot-on;
};
/* L1 - VDD_MX */
pm2250_l2: l2 {
/* LPDDR4X VDD2 */
regulator-min-microvolts = <1136000>;
regulator-max-microvolts = <1136000>;
regulator-always-on;
regulator-boot-on;
};
pm2250_l3: l3 {
/* LPDDR4X VDDQ */
regulator-min-microvolts = <616000>;
regulator-max-microvolts = <616000>;
regulator-always-on;
regulator-boot-on;
};
pm2250_l4: l4 {
/* max = 3.05V -> max = just below 3V (SDHCI2) */
regulator-min-microvolts = <1648000>;
regulator-max-microvolts = <2992000>;
regulator-allow-set-load;
};
pm2250_l5: l5 {
/* CSI/DSI */
regulator-min-microvolts = <1232000>;
regulator-max-microvolts = <1232000>;
regulator-allow-set-load;
regulator-boot-on;
};
pm2250_l6: l6 {
/* DRAM PLL */
regulator-min-microvolts = <928000>;
regulator-max-microvolts = <928000>;
regulator-always-on;
regulator-boot-on;
};
pm2250_l7: l7 {
/* Wi-Fi CX/MX */
regulator-min-microvolts = <664000>;
regulator-max-microvolts = <664000>;
};
/*
* L8 - VDD_LPI_CX
* L9 - VDD_LPI_MX
*/
pm2250_l10: l10 {
/* Wi-Fi RFA */
regulator-min-microvolts = <1300000>;
regulator-max-microvolts = <1300000>;
};
pm2250_l11: l11 {
/* GPS RF1 */
regulator-min-microvolts = <1000000>;
regulator-max-microvolts = <1000000>;
regulator-boot-on;
};
pm2250_l12: l12 {
/* USB PHYs */
regulator-min-microvolts = <928000>;
regulator-max-microvolts = <928000>;
regulator-allow-set-load;
regulator-boot-on;
};
pm2250_l13: l13 {
/* USB/QFPROM/PLLs */
regulator-min-microvolts = <1800000>;
regulator-max-microvolts = <1800000>;
regulator-allow-set-load;
regulator-boot-on;
};
pm2250_l14: l14 {
/* SDHCI1 VQMMC */
regulator-min-microvolts = <1800000>;
regulator-max-microvolts = <1800000>;
regulator-allow-set-load;
/* Broken hardware, never turn it off! */
regulator-always-on;
};
pm2250_l15: l15 {
/* WCD/DSI/BT VDDIO */
regulator-min-microvolts = <1800000>;
regulator-max-microvolts = <1800000>;
regulator-allow-set-load;
regulator-always-on;
regulator-boot-on;
};
pm2250_l16: l16 {
/* GPS RF2 */
regulator-min-microvolts = <1800000>;
regulator-max-microvolts = <1800000>;
regulator-boot-on;
};
pm2250_l17: l17 {
regulator-min-microvolts = <3000000>;
regulator-max-microvolts = <3000000>;
};
pm2250_l18: l18 {
/* VDD_PXn */
regulator-min-microvolts = <1800000>;
regulator-max-microvolts = <1800000>;
};
pm2250_l19: l19 {
/* VDD_PXn */
regulator-min-microvolts = <1800000>;
regulator-max-microvolts = <1800000>;
};
pm2250_l20: l20 {
/* SDHCI1 VMMC */
regulator-min-microvolts = <2856000>;
regulator-max-microvolts = <2856000>;
regulator-allow-set-load;
};
pm2250_l21: l21 {
/* SDHCI2 VMMC */
regulator-min-microvolts = <2960000>;
regulator-max-microvolts = <3300000>;
regulator-allow-set-load;
regulator-boot-on;
};
pm2250_l22: l22 {
/* Wi-Fi */
regulator-min-microvolts = <3312000>;
regulator-max-microvolts = <3312000>;
};
};
};
&sdhc_1 {
vmmc-supply = <&pm2250_l20>;
vqmmc-supply = <&pm2250_l14>;
pinctrl-0 = <&sdc1_state_on>;
pinctrl-1 = <&sdc1_state_off>;
pinctrl-names = "default", "sleep";
@ -61,6 +322,8 @@
};
&sdhc_2 {
vmmc-supply = <&pm2250_l21>;
vqmmc-supply = <&pm2250_l4>;
cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&sdc2_state_on &sd_det_in_on>;
pinctrl-1 = <&sdc2_state_off &sd_det_in_off>;
@ -104,6 +367,9 @@
};
&usb_hsphy {
vdd-supply = <&pm2250_l12>;
vdda-pll-supply = <&pm2250_l13>;
vdda-phy-dpdm-supply = <&pm2250_l21>;
status = "okay";
};

8
arch/arm64/boot/dts/qcom/qrb4210-rb2.dts
View File

@ -179,6 +179,14 @@
status = "okay";
};
&gpu {
status = "okay";
zap-shader {
firmware-name = "qcom/qrb4210/a610_zap.mbn";
};
};
&i2c2 {
clock-frequency = <400000>;
status = "okay";

15
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
View File

@ -640,16 +640,18 @@
};
&pm8150_adc {
xo-therm@4c {
channel@4c {
reg = <ADC5_XO_THERM_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
label = "xo_therm";
};
wifi-therm@4e {
channel@4e {
reg = <ADC5_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
label = "wifi_therm";
};
};
@ -717,10 +719,11 @@
};
&pm8150b_adc {
conn-therm@4f {
channel@4f {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
label = "conn_therm";
};
};
@ -752,16 +755,18 @@
};
&pm8150l_adc {
skin-msm-therm@4e {
channel@4e {
reg = <ADC5_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
label = "skin_msm_therm";
};
pm8150l-therm@4f {
channel@4f {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
label = "pm8150l_therm";
};
};

16
arch/arm64/boot/dts/qcom/qru1000-idp.dts
View File

@ -448,6 +448,22 @@
status = "okay";
};
&reserved_memory {
ecc_meta_data_mem: ecc-meta-data@f0000000 {
reg = <0x0 0xf0000000 0x0 0x10000000>;
no-map;
};
tenx_sp_mem: tenx-sp-buffer@800000000 {
reg = <0x8 0x0 0x0 0x80000000>;
no-map;
};
};
&tlmm {
gpio-reserved-ranges = <28 2>;
};
&uart7 {
status = "okay";
};

11
arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi
View File

@ -14,7 +14,7 @@
#address-cells = <1>;
#size-cells = <0>;
rtc@6000 {
pmm8540a_rtc: rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>, <0x6100>;
reg-names = "rtc", "alarm";
@ -39,6 +39,15 @@
#address-cells = <1>;
#size-cells = <0>;
pmm8540c_sdam_2: nvram@b110 {
compatible = "qcom,spmi-sdam";
reg = <0xb110>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xb110 0xb0>;
status = "disabled";
};
pmm8540c_gpios: gpio@c000 {
compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
reg = <0xc000>;

15
arch/arm64/boot/dts/qcom/sa8540p-ride.dts
View File

@ -407,6 +407,21 @@
status = "okay";
};
&pmm8540a_rtc {
nvmem-cells = <&rtc_offset>;
nvmem-cell-names = "offset";
status = "okay";
};
&pmm8540c_sdam_2 {
status = "okay";
rtc_offset: rtc-offset@a0 {
reg = <0xa0 0x4>;
};
};
&qup0 {
status = "okay";
};

2
arch/arm64/boot/dts/qcom/sa8540p.dtsi
View File

@ -207,7 +207,7 @@
linux,pci-domain = <2>;
interrupts = <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,

279
arch/arm64/boot/dts/qcom/sa8775p-ride.dts
View File

@ -16,11 +16,13 @@
compatible = "qcom,sa8775p-ride", "qcom,sa8775p";
aliases {
ethernet0 = &ethernet0;
ethernet1 = &ethernet1;
i2c11 = &i2c11;
i2c18 = &i2c18;
serial0 = &uart10;
serial1 = &uart12;
serial2 = &uart17;
i2c11 = &i2c11;
i2c18 = &i2c18;
spi16 = &spi16;
ufshc1 = &ufs_mem_hc;
};
@ -261,6 +263,173 @@
};
};
&ethernet0 {
phy-mode = "sgmii";
phy-handle = <&sgmii_phy0>;
pinctrl-0 = <&ethernet0_default>;
pinctrl-names = "default";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
snps,ps-speed = <1000>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
sgmii_phy0: phy@8 {
compatible = "ethernet-phy-id0141.0dd4";
reg = <0x8>;
device_type = "ethernet-phy";
reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
sgmii_phy1: phy@a {
compatible = "ethernet-phy-id0141.0dd4";
reg = <0xa>;
device_type = "ethernet-phy";
reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,route-up;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
snps,route-ptp;
};
queue2 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x2>;
snps,route-avcp;
};
queue3 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x3>;
snps,priority = <0xc>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <4>;
snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,dcb-algorithm;
};
queue2 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
queue3 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
};
};
&ethernet1 {
phy-mode = "sgmii";
phy-handle = <&sgmii_phy1>;
snps,mtl-rx-config = <&mtl_rx_setup1>;
snps,mtl-tx-config = <&mtl_tx_setup1>;
snps,ps-speed = <1000>;
status = "okay";
mtl_rx_setup1: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,route-up;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
snps,route-ptp;
};
queue2 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x2>;
snps,route-avcp;
};
queue3 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x3>;
snps,priority = <0xc>;
};
};
mtl_tx_setup1: tx-queues-config {
snps,tx-queues-to-use = <4>;
snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,dcb-algorithm;
};
queue2 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
queue3 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
};
};
&i2c11 {
clock-frequency = <400000>;
pinctrl-0 = <&qup_i2c11_default>;
@ -355,6 +524,16 @@
status = "okay";
};
&serdes0 {
phy-supply = <&vreg_l5a>;
status = "okay";
};
&serdes1 {
phy-supply = <&vreg_l5a>;
status = "okay";
};
&sleep_clk {
clock-frequency = <32764>;
};
@ -366,6 +545,22 @@
};
&tlmm {
ethernet0_default: ethernet0-default-state {
ethernet0_mdc: ethernet0-mdc-pins {
pins = "gpio8";
function = "emac0_mdc";
drive-strength = <16>;
bias-pull-up;
};
ethernet0_mdio: ethernet0-mdio-pins {
pins = "gpio9";
function = "emac0_mdio";
drive-strength = <16>;
bias-pull-up;
};
};
qup_uart10_default: qup-uart10-state {
pins = "gpio46", "gpio47";
function = "qup1_se3";
@ -443,6 +638,86 @@
bias-pull-down;
};
};
pcie0_default_state: pcie0-default-state {
perst-pins {
pins = "gpio2";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq-pins {
pins = "gpio1";
function = "pcie0_clkreq";
drive-strength = <2>;
bias-pull-up;
};
wake-pins {
pins = "gpio0";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie1_default_state: pcie1-default-state {
perst-pins {
pins = "gpio4";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq-pins {
pins = "gpio3";
function = "pcie1_clkreq";
drive-strength = <2>;
bias-pull-up;
};
wake-pins {
pins = "gpio5";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};
&pcie0 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
status = "okay";
};
&pcie1 {
perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
status = "okay";
};
&pcie0_phy {
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l1c>;
status = "okay";
};
&pcie1_phy {
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l1c>;
status = "okay";
};
&uart10 {

289
arch/arm64/boot/dts/qcom/sa8775p.dtsi
View File

@ -481,8 +481,8 @@
<0>,
<0>,
<0>,
<0>,
<0>,
<&pcie0_phy>,
<&pcie1_phy>,
<0>,
<0>,
<0>;
@ -1837,6 +1837,24 @@
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
};
serdes0: phy@8901000 {
compatible = "qcom,sa8775p-dwmac-sgmii-phy";
reg = <0x0 0x08901000 0x0 0xe10>;
clocks = <&gcc GCC_SGMI_CLKREF_EN>;
clock-names = "sgmi_ref";
#phy-cells = <0>;
status = "disabled";
};
serdes1: phy@8902000 {
compatible = "qcom,sa8775p-dwmac-sgmii-phy";
reg = <0x0 0x08902000 0x0 0xe10>;
clocks = <&gcc GCC_SGMI_CLKREF_EN>;
clock-names = "sgmi_ref";
#phy-cells = <0>;
status = "disabled";
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sa8775p-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x30000>,
@ -1925,6 +1943,7 @@
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 149>;
wakeup-parent = <&pdc>;
};
apps_smmu: iommu@15000000 {
@ -2306,6 +2325,72 @@
#freq-domain-cells = <1>;
};
ethernet1: ethernet@23000000 {
compatible = "qcom,sa8775p-ethqos";
reg = <0x0 0x23000000 0x0 0x10000>,
<0x0 0x23016000 0x0 0x100>;
reg-names = "stmmaceth", "rgmii";
interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&gcc GCC_EMAC1_AXI_CLK>,
<&gcc GCC_EMAC1_SLV_AHB_CLK>,
<&gcc GCC_EMAC1_PTP_CLK>,
<&gcc GCC_EMAC1_PHY_AUX_CLK>;
clock-names = "stmmaceth",
"pclk",
"ptp_ref",
"phyaux";
power-domains = <&gcc EMAC1_GDSC>;
phys = <&serdes1>;
phy-names = "serdes";
iommus = <&apps_smmu 0x140 0xf>;
snps,tso;
snps,pbl = <32>;
rx-fifo-depth = <16384>;
tx-fifo-depth = <16384>;
status = "disabled";
};
ethernet0: ethernet@23040000 {
compatible = "qcom,sa8775p-ethqos";
reg = <0x0 0x23040000 0x0 0x10000>,
<0x0 0x23056000 0x0 0x100>;
reg-names = "stmmaceth", "rgmii";
interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&gcc GCC_EMAC0_AXI_CLK>,
<&gcc GCC_EMAC0_SLV_AHB_CLK>,
<&gcc GCC_EMAC0_PTP_CLK>,
<&gcc GCC_EMAC0_PHY_AUX_CLK>;
clock-names = "stmmaceth",
"pclk",
"ptp_ref",
"phyaux";
power-domains = <&gcc EMAC0_GDSC>;
phys = <&serdes0>;
phy-names = "serdes";
iommus = <&apps_smmu 0x120 0xf>;
snps,tso;
snps,pbl = <32>;
rx-fifo-depth = <16384>;
tx-fifo-depth = <16384>;
status = "disabled";
};
};
arch_timer: timer {
@ -2315,4 +2400,204 @@
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
pcie0: pci@1c00000{
compatible = "qcom,pcie-sa8775p";
reg = <0x0 0x01c00000 0x0 0x3000>,
<0x0 0x40000000 0x0 0xf20>,
<0x0 0x40000f20 0x0 0xa8>,
<0x0 0x40001000 0x0 0x4000>,
<0x0 0x40100000 0x0 0x100000>,
<0x0 0x01c03000 0x0 0x1000>;
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
bus-range = <0x00 0xff>;
dma-coherent;
linux,pci-domain = <0>;
num-lanes = <2>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
clock-names = "aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a";
assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
assigned-clock-rates = <19200000>;
interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
<0x100 &pcie_smmu 0x0001 0x1>;
resets = <&gcc GCC_PCIE_0_BCR>;
reset-names = "pci";
power-domains = <&gcc PCIE_0_GDSC>;
phys = <&pcie0_phy>;
phy-names = "pciephy";
status = "disabled";
};
pcie0_phy: phy@1c04000 {
compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
reg = <0x0 0x1c04000 0x0 0x2000>;
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_CLKREF_EN>,
<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
<&gcc GCC_PCIE_0_PHY_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
"pipediv2", "phy_aux";
assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "phy";
#clock-cells = <0>;
clock-output-names = "pcie_0_pipe_clk";
#phy-cells = <0>;
status = "disabled";
};
pcie1: pci@1c10000{
compatible = "qcom,pcie-sa8775p";
reg = <0x0 0x01c10000 0x0 0x3000>,
<0x0 0x60000000 0x0 0xf20>,
<0x0 0x60000f20 0x0 0xa8>,
<0x0 0x60001000 0x0 0x4000>,
<0x0 0x60100000 0x0 0x100000>,
<0x0 0x01c13000 0x0 0x1000>;
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
bus-range = <0x00 0xff>;
dma-coherent;
linux,pci-domain = <1>;
num-lanes = <4>;
interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
clock-names = "aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a";
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
assigned-clock-rates = <19200000>;
interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
<0x100 &pcie_smmu 0x0081 0x1>;
resets = <&gcc GCC_PCIE_1_BCR>;
reset-names = "pci";
power-domains = <&gcc PCIE_1_GDSC>;
phys = <&pcie1_phy>;
phy-names = "pciephy";
status = "disabled";
};
pcie1_phy: phy@1c14000 {
compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
reg = <0x0 0x1c14000 0x0 0x4000>;
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_CLKREF_EN>,
<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK>,
<&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
<&gcc GCC_PCIE_1_PHY_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
"pipediv2", "phy_aux";
assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "phy";
#clock-cells = <0>;
clock-output-names = "pcie_1_pipe_clk";
#phy-cells = <0>;
status = "disabled";
};
};

6
arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
View File

@ -314,16 +314,18 @@
};
&pm6150_adc {
thermistor@4e {
channel@4e {
reg = <ADC5_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
label = "thermistor";
};
charger-thermistor@4f {
channel@4f {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
label = "charger_thermistor";
};
};

107
arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi Normal file
View File

@ -0,0 +1,107 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Devices that use SC7180 with TrustedFirmware-A
* need PSCI PC mode instead of the OSI mode provided
* by Qualcomm firmware.
*/
&CPU0 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
};
&CPU1 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
};
&CPU2 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
};
&CPU3 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
};
&CPU4 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
};
&CPU5 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
};
&CPU6 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
};
&CPU7 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
};
/delete-node/ &domain_idle_states;
&idle_states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "cluster-power-down";
arm,psci-suspend-param = <0x40003444>;
entry-latency-us = <3263>;
exit-latency-us = <6562>;
min-residency-us = <9926>;
local-timer-stop;
};
};
/delete-node/ &CPU_PD0;
/delete-node/ &CPU_PD1;
/delete-node/ &CPU_PD2;
/delete-node/ &CPU_PD3;
/delete-node/ &CPU_PD4;
/delete-node/ &CPU_PD5;
/delete-node/ &CPU_PD6;
/delete-node/ &CPU_PD7;
/delete-node/ &CLUSTER_PD;
&apps_rsc {
/delete-property/ power-domains;
};

1
arch/arm64/boot/dts/qcom/sc7180-idp.dts
View File

@ -11,6 +11,7 @@
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include "sc7180.dtsi"
#include "sc7180-firmware-tfa.dtsi"
#include "pm6150.dtsi"
#include "pm6150l.dtsi"

4
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts
View File

@ -24,8 +24,8 @@
};
&pm6150_adc {
/delete-node/ skin-temp-thermistor@4e;
/delete-node/ charger-thermistor@4f;
/delete-node/ channel@4e;
/delete-node/ channel@4f;
};
&pm6150_adc_tm {

3
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
View File

@ -119,10 +119,11 @@ ap_ts_pen_1v8: &i2c4 {
};
&pm6150_adc {
skin-temp-thermistor@4e {
channel@4e {
reg = <ADC5_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
label = "skin_therm";
};
};

3
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
View File

@ -145,10 +145,11 @@ ap_ts_pen_1v8: &i2c4 {
};
&pm6150_adc {
skin-temp-thermistor@4d {
channel@4d {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
label = "skin_therm";
};
};

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