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MIPS: KVM: Trace guest register access emulation
Trace emulation of guest access to various registers via MFC0/MTC0/DMFC0/DMTC0 instructions (coprocessor 0) and the RDHWR instruction (hardware registers exposed to userland), replacing some existing kvm_debug calls. Trace events are much more practical for this kind of debug output. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -979,7 +979,6 @@ enum emulation_result kvm_mips_emulate_CP0(u32 inst, u32 *opc, u32 cause,
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struct mips_coproc *cop0 = vcpu->arch.cop0;
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enum emulation_result er = EMULATE_DONE;
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u32 rt, rd, copz, sel, co_bit, op;
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unsigned long pc = vcpu->arch.pc;
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unsigned long curr_pc;
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/*
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@ -1046,20 +1045,27 @@ enum emulation_result kvm_mips_emulate_CP0(u32 inst, u32 *opc, u32 cause,
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#endif
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}
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kvm_debug
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("[%#lx] MFCz[%d][%d], vcpu->arch.gprs[%d]: %#lx\n",
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pc, rd, sel, rt, vcpu->arch.gprs[rt]);
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trace_kvm_hwr(vcpu, KVM_TRACE_MFC0,
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KVM_TRACE_COP0(rd, sel),
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vcpu->arch.gprs[rt]);
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break;
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case dmfc_op:
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vcpu->arch.gprs[rt] = cop0->reg[rd][sel];
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trace_kvm_hwr(vcpu, KVM_TRACE_DMFC0,
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KVM_TRACE_COP0(rd, sel),
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vcpu->arch.gprs[rt]);
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break;
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case mtc_op:
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#ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
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cop0->stat[rd][sel]++;
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#endif
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trace_kvm_hwr(vcpu, KVM_TRACE_MTC0,
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KVM_TRACE_COP0(rd, sel),
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vcpu->arch.gprs[rt]);
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if ((rd == MIPS_CP0_TLB_INDEX)
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&& (vcpu->arch.gprs[rt] >=
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KVM_MIPS_GUEST_TLB_SIZE)) {
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@ -1098,10 +1104,6 @@ enum emulation_result kvm_mips_emulate_CP0(u32 inst, u32 *opc, u32 cause,
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kvm_mips_write_count(vcpu, vcpu->arch.gprs[rt]);
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goto done;
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} else if ((rd == MIPS_CP0_COMPARE) && (sel == 0)) {
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kvm_debug("[%#lx] MTCz, COMPARE %#lx <- %#lx\n",
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pc, kvm_read_c0_guest_compare(cop0),
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vcpu->arch.gprs[rt]);
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/* If we are writing to COMPARE */
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/* Clear pending timer interrupt, if any */
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kvm_mips_write_compare(vcpu,
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@ -1237,14 +1239,14 @@ enum emulation_result kvm_mips_emulate_CP0(u32 inst, u32 *opc, u32 cause,
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kvm_mips_trans_mtc0(inst, opc, vcpu);
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#endif
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}
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kvm_debug("[%#lx] MTCz, cop0->reg[%d][%d]: %#lx\n", pc,
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rd, sel, cop0->reg[rd][sel]);
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break;
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case dmtc_op:
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kvm_err("!!!!!!![%#lx]dmtc_op: rt: %d, rd: %d, sel: %d!!!!!!\n",
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vcpu->arch.pc, rt, rd, sel);
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trace_kvm_hwr(vcpu, KVM_TRACE_DMTC0,
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KVM_TRACE_COP0(rd, sel),
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vcpu->arch.gprs[rt]);
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er = EMULATE_FAIL;
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break;
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@ -2307,6 +2309,8 @@ enum emulation_result kvm_mips_handle_ri(u32 cause, u32 *opc,
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int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
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int rd = (inst & RD) >> 11;
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int rt = (inst & RT) >> 16;
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int sel = (inst >> 6) & 0x7;
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/* If usermode, check RDHWR rd is allowed by guest HWREna */
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if (usermode && !(kvm_read_c0_guest_hwrena(cop0) & BIT(rd))) {
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kvm_debug("RDHWR %#x disallowed by HWREna @ %p\n",
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@ -2342,6 +2346,9 @@ enum emulation_result kvm_mips_handle_ri(u32 cause, u32 *opc,
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kvm_debug("RDHWR %#x not supported @ %p\n", rd, opc);
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goto emulate_ri;
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}
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trace_kvm_hwr(vcpu, KVM_TRACE_RDHWR, KVM_TRACE_HWR(rd, sel),
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vcpu->arch.gprs[rt]);
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} else {
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kvm_debug("Emulate RI not supported @ %p: %#x\n", opc, inst);
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goto emulate_ri;
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@ -124,6 +124,94 @@ TRACE_EVENT(kvm_exit,
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__entry->pc)
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);
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#define KVM_TRACE_MFC0 0
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#define KVM_TRACE_MTC0 1
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#define KVM_TRACE_DMFC0 2
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#define KVM_TRACE_DMTC0 3
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#define KVM_TRACE_RDHWR 4
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#define KVM_TRACE_HWR_COP0 0
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#define KVM_TRACE_HWR_HWR 1
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#define KVM_TRACE_COP0(REG, SEL) ((KVM_TRACE_HWR_COP0 << 8) | \
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((REG) << 3) | (SEL))
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#define KVM_TRACE_HWR(REG, SEL) ((KVM_TRACE_HWR_HWR << 8) | \
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((REG) << 3) | (SEL))
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#define kvm_trace_symbol_hwr_ops \
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{ KVM_TRACE_MFC0, "MFC0" }, \
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{ KVM_TRACE_MTC0, "MTC0" }, \
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{ KVM_TRACE_DMFC0, "DMFC0" }, \
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{ KVM_TRACE_DMTC0, "DMTC0" }, \
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{ KVM_TRACE_RDHWR, "RDHWR" }
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#define kvm_trace_symbol_hwr_cop \
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{ KVM_TRACE_HWR_COP0, "COP0" }, \
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{ KVM_TRACE_HWR_HWR, "HWR" }
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#define kvm_trace_symbol_hwr_regs \
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{ KVM_TRACE_COP0( 0, 0), "Index" }, \
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{ KVM_TRACE_COP0( 2, 0), "EntryLo0" }, \
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{ KVM_TRACE_COP0( 3, 0), "EntryLo1" }, \
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{ KVM_TRACE_COP0( 4, 0), "Context" }, \
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{ KVM_TRACE_COP0( 4, 2), "UserLocal" }, \
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{ KVM_TRACE_COP0( 5, 0), "PageMask" }, \
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{ KVM_TRACE_COP0( 6, 0), "Wired" }, \
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{ KVM_TRACE_COP0( 7, 0), "HWREna" }, \
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{ KVM_TRACE_COP0( 8, 0), "BadVAddr" }, \
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{ KVM_TRACE_COP0( 9, 0), "Count" }, \
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{ KVM_TRACE_COP0(10, 0), "EntryHi" }, \
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{ KVM_TRACE_COP0(11, 0), "Compare" }, \
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{ KVM_TRACE_COP0(12, 0), "Status" }, \
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{ KVM_TRACE_COP0(12, 1), "IntCtl" }, \
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{ KVM_TRACE_COP0(12, 2), "SRSCtl" }, \
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{ KVM_TRACE_COP0(13, 0), "Cause" }, \
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{ KVM_TRACE_COP0(14, 0), "EPC" }, \
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{ KVM_TRACE_COP0(15, 0), "PRId" }, \
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{ KVM_TRACE_COP0(15, 1), "EBase" }, \
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{ KVM_TRACE_COP0(16, 0), "Config" }, \
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{ KVM_TRACE_COP0(16, 1), "Config1" }, \
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{ KVM_TRACE_COP0(16, 2), "Config2" }, \
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{ KVM_TRACE_COP0(16, 3), "Config3" }, \
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{ KVM_TRACE_COP0(16, 4), "Config4" }, \
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{ KVM_TRACE_COP0(16, 5), "Config5" }, \
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{ KVM_TRACE_COP0(16, 7), "Config7" }, \
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{ KVM_TRACE_COP0(26, 0), "ECC" }, \
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{ KVM_TRACE_COP0(30, 0), "ErrorEPC" }, \
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{ KVM_TRACE_HWR( 0, 0), "CPUNum" }, \
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{ KVM_TRACE_HWR( 1, 0), "SYNCI_Step" }, \
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{ KVM_TRACE_HWR( 2, 0), "CC" }, \
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{ KVM_TRACE_HWR( 3, 0), "CCRes" }, \
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{ KVM_TRACE_HWR(29, 0), "ULR" }
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TRACE_EVENT(kvm_hwr,
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TP_PROTO(struct kvm_vcpu *vcpu, unsigned int op, unsigned int reg,
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unsigned long val),
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TP_ARGS(vcpu, op, reg, val),
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TP_STRUCT__entry(
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__field(unsigned long, val)
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__field(u16, reg)
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__field(u8, op)
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),
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TP_fast_assign(
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__entry->val = val;
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__entry->reg = reg;
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__entry->op = op;
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),
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TP_printk("%s %s (%s:%u:%u) 0x%08lx",
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__print_symbolic(__entry->op,
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kvm_trace_symbol_hwr_ops),
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__print_symbolic(__entry->reg,
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kvm_trace_symbol_hwr_regs),
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__print_symbolic(__entry->reg >> 8,
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kvm_trace_symbol_hwr_cop),
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(__entry->reg >> 3) & 0x1f,
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__entry->reg & 0x7,
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__entry->val)
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);
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#define KVM_TRACE_AUX_RESTORE 0
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#define KVM_TRACE_AUX_SAVE 1
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#define KVM_TRACE_AUX_ENABLE 2
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