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powerpc/powernv: remove the unused pnv_pci_set_p2p function

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This function has never been used anywhere in the kernel tree since it
was added to the tree.  We also now have proper PCIe P2P APIs in the core
kernel, and any new P2P support should be using those.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Christoph Hellwig 2019-06-25 16:52:36 +02:00 committed by Michael Ellerman
parent aaf06665f7
commit 6398261866
5 changed files with 0 additions and 84 deletions
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2
arch/powerpc/include/asm/opal.h
View File

@ -287,8 +287,6 @@ int64_t opal_xive_set_queue_state(uint64_t vp, uint32_t prio,
uint32_t qtoggle, uint32_t qtoggle,
uint32_t qindex); uint32_t qindex);
int64_t opal_xive_get_vp_state(uint64_t vp, __be64 *out_w01); int64_t opal_xive_get_vp_state(uint64_t vp, __be64 *out_w01);
int64_t opal_pci_set_p2p(uint64_t phb_init, uint64_t phb_target,
uint64_t desc, uint16_t pe_number);
int64_t opal_imc_counters_init(uint32_t type, uint64_t address, int64_t opal_imc_counters_init(uint32_t type, uint64_t address,
uint64_t cpu_pir); uint64_t cpu_pir);

2
arch/powerpc/include/asm/pnv-pci.h
View File

@ -26,8 +26,6 @@ extern int pnv_pci_get_presence_state(uint64_t id, uint8_t *state);
extern int pnv_pci_get_power_state(uint64_t id, uint8_t *state); extern int pnv_pci_get_power_state(uint64_t id, uint8_t *state);
extern int pnv_pci_set_power_state(uint64_t id, uint8_t state, extern int pnv_pci_set_power_state(uint64_t id, uint8_t state,
struct opal_msg *msg); struct opal_msg *msg);
extern int pnv_pci_set_p2p(struct pci_dev *initiator, struct pci_dev *target,
u64 desc);
extern int pnv_pci_enable_tunnel(struct pci_dev *dev, uint64_t *asnind); extern int pnv_pci_enable_tunnel(struct pci_dev *dev, uint64_t *asnind);
extern int pnv_pci_disable_tunnel(struct pci_dev *dev); extern int pnv_pci_disable_tunnel(struct pci_dev *dev);

1
arch/powerpc/platforms/powernv/opal-call.c
View File

@ -273,7 +273,6 @@ OPAL_CALL(opal_npu_map_lpar, OPAL_NPU_MAP_LPAR);
OPAL_CALL(opal_imc_counters_init, OPAL_IMC_COUNTERS_INIT); OPAL_CALL(opal_imc_counters_init, OPAL_IMC_COUNTERS_INIT);
OPAL_CALL(opal_imc_counters_start, OPAL_IMC_COUNTERS_START); OPAL_CALL(opal_imc_counters_start, OPAL_IMC_COUNTERS_START);
OPAL_CALL(opal_imc_counters_stop, OPAL_IMC_COUNTERS_STOP); OPAL_CALL(opal_imc_counters_stop, OPAL_IMC_COUNTERS_STOP);
OPAL_CALL(opal_pci_set_p2p, OPAL_PCI_SET_P2P);
OPAL_CALL(opal_get_powercap, OPAL_GET_POWERCAP); OPAL_CALL(opal_get_powercap, OPAL_GET_POWERCAP);
OPAL_CALL(opal_set_powercap, OPAL_SET_POWERCAP); OPAL_CALL(opal_set_powercap, OPAL_SET_POWERCAP);
OPAL_CALL(opal_get_power_shift_ratio, OPAL_GET_POWER_SHIFT_RATIO); OPAL_CALL(opal_get_power_shift_ratio, OPAL_GET_POWER_SHIFT_RATIO);

74
arch/powerpc/platforms/powernv/pci.c
View File

@ -38,7 +38,6 @@
#include "powernv.h" #include "powernv.h"
#include "pci.h" #include "pci.h"
static DEFINE_MUTEX(p2p_mutex);
static DEFINE_MUTEX(tunnel_mutex); static DEFINE_MUTEX(tunnel_mutex);
int pnv_pci_get_slot_id(struct device_node *np, uint64_t *id) int pnv_pci_get_slot_id(struct device_node *np, uint64_t *id)
@ -861,79 +860,6 @@ void pnv_pci_dma_bus_setup(struct pci_bus *bus)
} }
} }
int pnv_pci_set_p2p(struct pci_dev *initiator, struct pci_dev *target, u64 desc)
{
struct pci_controller *hose;
struct pnv_phb *phb_init, *phb_target;
struct pnv_ioda_pe *pe_init;
int rc;
if (!opal_check_token(OPAL_PCI_SET_P2P))
return -ENXIO;
hose = pci_bus_to_host(initiator->bus);
phb_init = hose->private_data;
hose = pci_bus_to_host(target->bus);
phb_target = hose->private_data;
pe_init = pnv_ioda_get_pe(initiator);
if (!pe_init)
return -ENODEV;
/*
* Configuring the initiator's PHB requires to adjust its
* TVE#1 setting. Since the same device can be an initiator
* several times for different target devices, we need to keep
* a reference count to know when we can restore the default
* bypass setting on its TVE#1 when disabling. Opal is not
* tracking PE states, so we add a reference count on the PE
* in linux.
*
* For the target, the configuration is per PHB, so we keep a
* target reference count on the PHB.
*/
mutex_lock(&p2p_mutex);
if (desc & OPAL_PCI_P2P_ENABLE) {
/* always go to opal to validate the configuration */
rc = opal_pci_set_p2p(phb_init->opal_id, phb_target->opal_id,
desc, pe_init->pe_number);
if (rc != OPAL_SUCCESS) {
rc = -EIO;
goto out;
}
pe_init->p2p_initiator_count++;
phb_target->p2p_target_count++;
} else {
if (!pe_init->p2p_initiator_count ||
!phb_target->p2p_target_count) {
rc = -EINVAL;
goto out;
}
if (--pe_init->p2p_initiator_count == 0)
pnv_pci_ioda2_set_bypass(pe_init, true);
if (--phb_target->p2p_target_count == 0) {
rc = opal_pci_set_p2p(phb_init->opal_id,
phb_target->opal_id, desc,
pe_init->pe_number);
if (rc != OPAL_SUCCESS) {
rc = -EIO;
goto out;
}
}
}
rc = 0;
out:
mutex_unlock(&p2p_mutex);
return rc;
}
EXPORT_SYMBOL_GPL(pnv_pci_set_p2p);
struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev) struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev)
{ {
struct pci_controller *hose = pci_bus_to_host(dev->bus); struct pci_controller *hose = pci_bus_to_host(dev->bus);

5
arch/powerpc/platforms/powernv/pci.h
View File

@ -79,9 +79,6 @@ struct pnv_ioda_pe {
struct pnv_ioda_pe *master; struct pnv_ioda_pe *master;
struct list_head slaves; struct list_head slaves;
/* PCI peer-to-peer*/
int p2p_initiator_count;
/* Link in list of PE#s */ /* Link in list of PE#s */
struct list_head list; struct list_head list;
}; };
@ -172,8 +169,6 @@ struct pnv_phb {
/* PHB and hub diagnostics */ /* PHB and hub diagnostics */
unsigned int diag_data_size; unsigned int diag_data_size;
u8 *diag_data; u8 *diag_data;
int p2p_target_count;
}; };
extern struct pci_ops pnv_pci_ops; extern struct pci_ops pnv_pci_ops;