Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-11-23 12:42:02 +00:00
Code Issues Packages Projects Releases Wiki Activity

perf powerpc: Refactor the code definition of perf reg extended mask in tools side header file

Browse Source 
PERF_REG_PMU_MASK_300 and PERF_REG_PMU_MASK_31 defines the mask value
for extended registers. Current definition of these mask values uses hex
constant and does not use registers by name, making it less readable.
Patch refactor the macro values in perf tools side header file by or'ing
together the actual register value constants.

Suggested-by: Michael Ellerman <mpe@ellerman.id.au>
Reviewed-by: Kajol Jain <kjain@linux.ibm.com>
Signed-off-by: Athira Jajeev <atrajeev@linux.vnet.ibm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Cc: Nageswara R Sastry <rnsastry@linux.ibm.com>
Cc: linuxppc-dev@lists.ozlabs.org
Link: https://lore.kernel.org/r/20211018114948.16830-2-atrajeev@linux.vnet.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Athira Rajeev 2021-10-18 17:19:47 +05:30 committed by Arnaldo Carvalho de Melo
parent 25900ea85c
commit 637b8b90fe
1 changed files with 13 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
tools/arch/powerpc/include/uapi/asm/perf_regs.h
View File

@ -61,27 +61,32 @@ enum perf_event_powerpc_regs {
PERF_REG_POWERPC_PMC4, PERF_REG_POWERPC_PMC4,
PERF_REG_POWERPC_PMC5, PERF_REG_POWERPC_PMC5,
PERF_REG_POWERPC_PMC6, PERF_REG_POWERPC_PMC6,
/* Max regs without the extended regs */ /* Max mask value for interrupt regs w/o extended regs */
PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1, PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1,
/* Max mask value for interrupt regs including extended regs */
PERF_REG_EXTENDED_MAX = PERF_REG_POWERPC_PMC6 + 1,
}; };
#define PERF_REG_PMU_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1) #define PERF_REG_PMU_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1)
/* Exclude MMCR3, SIER2, SIER3 for CPU_FTR_ARCH_300 */
#define PERF_EXCLUDE_REG_EXT_300 (7ULL << PERF_REG_POWERPC_MMCR3)
/* /*
* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300 * PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300
* includes 9 SPRS from MMCR0 to PMC6 excluding the * includes 9 SPRS from MMCR0 to PMC6 excluding the
* unsupported SPRS in PERF_EXCLUDE_REG_EXT_300. * unsupported SPRS MMCR3, SIER2 and SIER3.
*/ */
#define PERF_REG_PMU_MASK_300 ((0xfffULL << PERF_REG_POWERPC_MMCR0) - PERF_EXCLUDE_REG_EXT_300) #define PERF_REG_PMU_MASK_300 \
((1ULL << PERF_REG_POWERPC_MMCR0) | (1ULL << PERF_REG_POWERPC_MMCR1) | \
(1ULL << PERF_REG_POWERPC_MMCR2) | (1ULL << PERF_REG_POWERPC_PMC1) | \
(1ULL << PERF_REG_POWERPC_PMC2) | (1ULL << PERF_REG_POWERPC_PMC3) | \
(1ULL << PERF_REG_POWERPC_PMC4) | (1ULL << PERF_REG_POWERPC_PMC5) | \
(1ULL << PERF_REG_POWERPC_PMC6))
/* /*
* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31 * PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31
* includes 12 SPRs from MMCR0 to PMC6. * includes 12 SPRs from MMCR0 to PMC6.
*/ */
#define PERF_REG_PMU_MASK_31 (0xfffULL << PERF_REG_POWERPC_MMCR0) #define PERF_REG_PMU_MASK_31 \
(PERF_REG_PMU_MASK_300 | (1ULL << PERF_REG_POWERPC_MMCR3) | \
(1ULL << PERF_REG_POWERPC_SIER2) | (1ULL << PERF_REG_POWERPC_SIER3))
#define PERF_REG_EXTENDED_MAX (PERF_REG_POWERPC_PMC6 + 1)
#endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */ #endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */