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drm/amdgpu: disable uvd and vce clockgating on Fiji

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Doesn't work properly yet.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2016-02-02 18:22:24 -05:00
parent dba280b20b
commit 6357b75a5c
1 changed files with 1 additions and 2 deletions
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3
drivers/gpu/drm/amd/amdgpu/vi.c
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@ -1443,8 +1443,7 @@ static int vi_common_early_init(void *handle)
break;
case CHIP_FIJI:
adev->has_uvd = true;
adev->cg_flags = AMDGPU_CG_SUPPORT_UVD_MGCG |
AMDGPU_CG_SUPPORT_VCE_MGCG;
adev->cg_flags = 0;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x3c;
break;