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PCI: kirin: Reorganize the PHY logic inside the driver
The pcie-kirin PCIe driver contains internally a PHY interface for Kirin 960. As the next patches will add support for using an external PHY driver, reorganize the driver in a way that the PHY part will be self-contained. This could be moved to a separate PHY driver, but a change like that would mean a non-backward-compatible DT schema change. Link: https://lore.kernel.org/r/ad2f4aa6bbb71d5c9af0139704672f75f12644fc.1634812676.git.mchehab+huawei@kernel.org Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Xiaowei Song <songxiaowei@hisilicon.com> Cc: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Mauro Carvalho Chehab
Bjorn Helgaas
parent
e4e737bb5c
commit
61d3754743
@ -28,26 +28,16 @@
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#define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
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#define REF_CLK_FREQ 100000000
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/* PCIe ELBI registers */
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#define SOC_PCIECTRL_CTRL0_ADDR 0x000
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#define SOC_PCIECTRL_CTRL1_ADDR 0x004
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#define SOC_PCIEPHY_CTRL2_ADDR 0x008
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#define SOC_PCIEPHY_CTRL3_ADDR 0x00c
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#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21)
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/* info located in APB */
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#define PCIE_APP_LTSSM_ENABLE 0x01c
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#define PCIE_APB_PHY_CTRL0 0x0
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#define PCIE_APB_PHY_CTRL1 0x4
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#define PCIE_APB_PHY_STATUS0 0x400
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#define PCIE_LINKUP_ENABLE (0x8020)
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#define PCIE_LTSSM_ENABLE_BIT (0x1 << 11)
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#define PIPE_CLK_STABLE (0x1 << 19)
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#define PHY_REF_PAD_BIT (0x1 << 8)
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#define PHY_PWR_DOWN_BIT (0x1 << 22)
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#define PHY_RST_ACK_BIT (0x1 << 16)
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/* info located in sysctrl */
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#define SCTRL_PCIE_CMOS_OFFSET 0x60
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@ -60,6 +50,29 @@
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#define PCIE_DEBOUNCE_PARAM 0xF0F400
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#define PCIE_OE_BYPASS (0x3 << 28)
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struct kirin_pcie {
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struct dw_pcie *pci;
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struct phy *phy;
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void __iomem *apb_base;
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void *phy_priv; /* Needed for Kirin 960 PHY */
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};
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/*
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* Kirin 960 PHY. Can't be split into a PHY driver without changing the
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* DT schema.
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*/
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#define REF_CLK_FREQ 100000000
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/* PHY info located in APB */
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#define PCIE_APB_PHY_CTRL0 0x0
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#define PCIE_APB_PHY_CTRL1 0x4
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#define PCIE_APB_PHY_STATUS0 0x400
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#define PIPE_CLK_STABLE BIT(19)
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#define PHY_REF_PAD_BIT BIT(8)
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#define PHY_PWR_DOWN_BIT BIT(22)
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#define PHY_RST_ACK_BIT BIT(16)
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/* peri_crg ctrl */
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#define CRGCTRL_PCIE_ASSERT_OFFSET 0x88
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#define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000
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@ -69,8 +82,6 @@
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#define REF_2_PERST_MAX 25000
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#define PERST_2_ACCESS_MIN 10000
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#define PERST_2_ACCESS_MAX 12000
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#define LINK_WAIT_MIN 900
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#define LINK_WAIT_MAX 1000
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#define PIPE_CLK_WAIT_MIN 550
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#define PIPE_CLK_WAIT_MAX 600
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#define TIME_CMOS_MIN 100
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@ -78,20 +89,248 @@
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#define TIME_PHY_PD_MIN 10
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#define TIME_PHY_PD_MAX 11
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struct kirin_pcie {
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struct dw_pcie *pci;
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void __iomem *apb_base;
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void __iomem *phy_base;
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struct hi3660_pcie_phy {
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struct device *dev;
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void __iomem *base;
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struct regmap *crgctrl;
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struct regmap *sysctrl;
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struct clk *apb_sys_clk;
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struct clk *apb_phy_clk;
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struct clk *phy_ref_clk;
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struct clk *pcie_aclk;
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struct clk *pcie_aux_clk;
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struct clk *aclk;
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struct clk *aux_clk;
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int gpio_id_reset;
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};
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/* Registers in PCIePHY */
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static inline void kirin_apb_phy_writel(struct hi3660_pcie_phy *hi3660_pcie_phy,
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u32 val, u32 reg)
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{
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writel(val, hi3660_pcie_phy->base + reg);
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}
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static inline u32 kirin_apb_phy_readl(struct hi3660_pcie_phy *hi3660_pcie_phy,
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u32 reg)
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{
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return readl(hi3660_pcie_phy->base + reg);
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}
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static int hi3660_pcie_phy_get_clk(struct hi3660_pcie_phy *phy)
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{
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struct device *dev = phy->dev;
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phy->phy_ref_clk = devm_clk_get(dev, "pcie_phy_ref");
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if (IS_ERR(phy->phy_ref_clk))
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return PTR_ERR(phy->phy_ref_clk);
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phy->aux_clk = devm_clk_get(dev, "pcie_aux");
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if (IS_ERR(phy->aux_clk))
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return PTR_ERR(phy->aux_clk);
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phy->apb_phy_clk = devm_clk_get(dev, "pcie_apb_phy");
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if (IS_ERR(phy->apb_phy_clk))
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return PTR_ERR(phy->apb_phy_clk);
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phy->apb_sys_clk = devm_clk_get(dev, "pcie_apb_sys");
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if (IS_ERR(phy->apb_sys_clk))
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return PTR_ERR(phy->apb_sys_clk);
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phy->aclk = devm_clk_get(dev, "pcie_aclk");
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if (IS_ERR(phy->aclk))
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return PTR_ERR(phy->aclk);
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return 0;
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}
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static int hi3660_pcie_phy_get_resource(struct hi3660_pcie_phy *phy)
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{
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struct device *dev = phy->dev;
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struct platform_device *pdev;
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/* registers */
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pdev = container_of(dev, struct platform_device, dev);
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phy->base = devm_platform_ioremap_resource_byname(pdev, "phy");
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if (IS_ERR(phy->base))
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return PTR_ERR(phy->base);
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phy->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl");
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if (IS_ERR(phy->crgctrl))
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return PTR_ERR(phy->crgctrl);
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phy->sysctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl");
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if (IS_ERR(phy->sysctrl))
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return PTR_ERR(phy->sysctrl);
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/* gpios */
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phy->gpio_id_reset = of_get_named_gpio(dev->of_node,
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"reset-gpios", 0);
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if (phy->gpio_id_reset == -EPROBE_DEFER) {
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return -EPROBE_DEFER;
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} else if (!gpio_is_valid(phy->gpio_id_reset)) {
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dev_err(phy->dev, "unable to get a valid gpio pin\n");
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return -ENODEV;
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}
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return 0;
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}
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static int hi3660_pcie_phy_start(struct hi3660_pcie_phy *phy)
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{
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struct device *dev = phy->dev;
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u32 reg_val;
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reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL1);
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reg_val &= ~PHY_REF_PAD_BIT;
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kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL1);
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reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL0);
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reg_val &= ~PHY_PWR_DOWN_BIT;
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kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL0);
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usleep_range(TIME_PHY_PD_MIN, TIME_PHY_PD_MAX);
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reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL1);
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reg_val &= ~PHY_RST_ACK_BIT;
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kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL1);
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usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX);
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reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_STATUS0);
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if (reg_val & PIPE_CLK_STABLE) {
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dev_err(dev, "PIPE clk is not stable\n");
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return -EINVAL;
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}
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return 0;
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}
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static void hi3660_pcie_phy_oe_enable(struct hi3660_pcie_phy *phy)
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{
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u32 val;
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regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
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val |= PCIE_DEBOUNCE_PARAM;
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val &= ~PCIE_OE_BYPASS;
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regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
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}
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static int hi3660_pcie_phy_clk_ctrl(struct hi3660_pcie_phy *phy, bool enable)
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{
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int ret = 0;
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if (!enable)
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goto close_clk;
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ret = clk_set_rate(phy->phy_ref_clk, REF_CLK_FREQ);
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if (ret)
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return ret;
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ret = clk_prepare_enable(phy->phy_ref_clk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(phy->apb_sys_clk);
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if (ret)
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goto apb_sys_fail;
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ret = clk_prepare_enable(phy->apb_phy_clk);
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if (ret)
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goto apb_phy_fail;
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ret = clk_prepare_enable(phy->aclk);
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if (ret)
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goto aclk_fail;
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ret = clk_prepare_enable(phy->aux_clk);
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if (ret)
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goto aux_clk_fail;
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return 0;
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close_clk:
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clk_disable_unprepare(phy->aux_clk);
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aux_clk_fail:
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clk_disable_unprepare(phy->aclk);
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aclk_fail:
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clk_disable_unprepare(phy->apb_phy_clk);
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apb_phy_fail:
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clk_disable_unprepare(phy->apb_sys_clk);
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apb_sys_fail:
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clk_disable_unprepare(phy->phy_ref_clk);
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return ret;
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}
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static int hi3660_pcie_phy_power_on(struct kirin_pcie *pcie)
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{
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struct hi3660_pcie_phy *phy = pcie->phy_priv;
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int ret;
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/* Power supply for Host */
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regmap_write(phy->sysctrl,
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SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
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usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX);
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hi3660_pcie_phy_oe_enable(phy);
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ret = hi3660_pcie_phy_clk_ctrl(phy, true);
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if (ret)
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return ret;
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/* ISO disable, PCIeCtrl, PHY assert and clk gate clear */
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regmap_write(phy->sysctrl,
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SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
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regmap_write(phy->crgctrl,
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CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT);
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regmap_write(phy->sysctrl,
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SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT);
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ret = hi3660_pcie_phy_start(phy);
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if (ret)
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goto disable_clks;
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/* perst assert Endpoint */
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if (!gpio_request(phy->gpio_id_reset, "pcie_perst")) {
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usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
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ret = gpio_direction_output(phy->gpio_id_reset, 1);
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if (ret)
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goto disable_clks;
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usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
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return 0;
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}
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disable_clks:
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hi3660_pcie_phy_clk_ctrl(phy, false);
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return ret;
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}
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static int hi3660_pcie_phy_init(struct platform_device *pdev,
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struct kirin_pcie *pcie)
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{
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struct device *dev = &pdev->dev;
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struct hi3660_pcie_phy *phy;
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int ret;
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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if (!phy)
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return -ENOMEM;
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pcie->phy_priv = phy;
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phy->dev = dev;
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/* registers */
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pdev = container_of(dev, struct platform_device, dev);
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ret = hi3660_pcie_phy_get_clk(phy);
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if (ret)
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return ret;
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return hi3660_pcie_phy_get_resource(phy);
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}
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/*
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* The non-PHY part starts here
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*/
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/* Registers in PCIeCTRL */
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static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie,
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u32 val, u32 reg)
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@ -104,46 +343,6 @@ static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg)
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return readl(kirin_pcie->apb_base + reg);
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}
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/* Registers in PCIePHY */
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static inline void kirin_apb_phy_writel(struct kirin_pcie *kirin_pcie,
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u32 val, u32 reg)
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{
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writel(val, kirin_pcie->phy_base + reg);
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}
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static inline u32 kirin_apb_phy_readl(struct kirin_pcie *kirin_pcie, u32 reg)
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{
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return readl(kirin_pcie->phy_base + reg);
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}
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static long kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie,
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struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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kirin_pcie->phy_ref_clk = devm_clk_get(dev, "pcie_phy_ref");
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if (IS_ERR(kirin_pcie->phy_ref_clk))
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return PTR_ERR(kirin_pcie->phy_ref_clk);
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kirin_pcie->pcie_aux_clk = devm_clk_get(dev, "pcie_aux");
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if (IS_ERR(kirin_pcie->pcie_aux_clk))
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return PTR_ERR(kirin_pcie->pcie_aux_clk);
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kirin_pcie->apb_phy_clk = devm_clk_get(dev, "pcie_apb_phy");
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if (IS_ERR(kirin_pcie->apb_phy_clk))
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return PTR_ERR(kirin_pcie->apb_phy_clk);
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kirin_pcie->apb_sys_clk = devm_clk_get(dev, "pcie_apb_sys");
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if (IS_ERR(kirin_pcie->apb_sys_clk))
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return PTR_ERR(kirin_pcie->apb_sys_clk);
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kirin_pcie->pcie_aclk = devm_clk_get(dev, "pcie_aclk");
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if (IS_ERR(kirin_pcie->pcie_aclk))
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return PTR_ERR(kirin_pcie->pcie_aclk);
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return 0;
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}
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static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
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struct platform_device *pdev)
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{
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@ -152,151 +351,9 @@ static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
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if (IS_ERR(kirin_pcie->apb_base))
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return PTR_ERR(kirin_pcie->apb_base);
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kirin_pcie->phy_base =
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devm_platform_ioremap_resource_byname(pdev, "phy");
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if (IS_ERR(kirin_pcie->phy_base))
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return PTR_ERR(kirin_pcie->phy_base);
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kirin_pcie->crgctrl =
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syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl");
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if (IS_ERR(kirin_pcie->crgctrl))
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return PTR_ERR(kirin_pcie->crgctrl);
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kirin_pcie->sysctrl =
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syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl");
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if (IS_ERR(kirin_pcie->sysctrl))
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return PTR_ERR(kirin_pcie->sysctrl);
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return 0;
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}
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static int kirin_pcie_phy_init(struct kirin_pcie *kirin_pcie)
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{
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struct device *dev = kirin_pcie->pci->dev;
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u32 reg_val;
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reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
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reg_val &= ~PHY_REF_PAD_BIT;
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kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
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reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL0);
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reg_val &= ~PHY_PWR_DOWN_BIT;
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kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL0);
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usleep_range(TIME_PHY_PD_MIN, TIME_PHY_PD_MAX);
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reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
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reg_val &= ~PHY_RST_ACK_BIT;
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kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
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usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX);
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||||
reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
|
||||
if (reg_val & PIPE_CLK_STABLE) {
|
||||
dev_err(dev, "PIPE clk is not stable\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void kirin_pcie_oe_enable(struct kirin_pcie *kirin_pcie)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
regmap_read(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
|
||||
val |= PCIE_DEBOUNCE_PARAM;
|
||||
val &= ~PCIE_OE_BYPASS;
|
||||
regmap_write(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
|
||||
}
|
||||
|
||||
static int kirin_pcie_clk_ctrl(struct kirin_pcie *kirin_pcie, bool enable)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (!enable)
|
||||
goto close_clk;
|
||||
|
||||
ret = clk_set_rate(kirin_pcie->phy_ref_clk, REF_CLK_FREQ);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_prepare_enable(kirin_pcie->phy_ref_clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_prepare_enable(kirin_pcie->apb_sys_clk);
|
||||
if (ret)
|
||||
goto apb_sys_fail;
|
||||
|
||||
ret = clk_prepare_enable(kirin_pcie->apb_phy_clk);
|
||||
if (ret)
|
||||
goto apb_phy_fail;
|
||||
|
||||
ret = clk_prepare_enable(kirin_pcie->pcie_aclk);
|
||||
if (ret)
|
||||
goto aclk_fail;
|
||||
|
||||
ret = clk_prepare_enable(kirin_pcie->pcie_aux_clk);
|
||||
if (ret)
|
||||
goto aux_clk_fail;
|
||||
|
||||
return 0;
|
||||
|
||||
close_clk:
|
||||
clk_disable_unprepare(kirin_pcie->pcie_aux_clk);
|
||||
aux_clk_fail:
|
||||
clk_disable_unprepare(kirin_pcie->pcie_aclk);
|
||||
aclk_fail:
|
||||
clk_disable_unprepare(kirin_pcie->apb_phy_clk);
|
||||
apb_phy_fail:
|
||||
clk_disable_unprepare(kirin_pcie->apb_sys_clk);
|
||||
apb_sys_fail:
|
||||
clk_disable_unprepare(kirin_pcie->phy_ref_clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int kirin_pcie_power_on(struct kirin_pcie *kirin_pcie)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Power supply for Host */
|
||||
regmap_write(kirin_pcie->sysctrl,
|
||||
SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
|
||||
usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX);
|
||||
kirin_pcie_oe_enable(kirin_pcie);
|
||||
|
||||
ret = kirin_pcie_clk_ctrl(kirin_pcie, true);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* ISO disable, PCIeCtrl, PHY assert and clk gate clear */
|
||||
regmap_write(kirin_pcie->sysctrl,
|
||||
SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
|
||||
regmap_write(kirin_pcie->crgctrl,
|
||||
CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT);
|
||||
regmap_write(kirin_pcie->sysctrl,
|
||||
SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT);
|
||||
|
||||
ret = kirin_pcie_phy_init(kirin_pcie);
|
||||
if (ret)
|
||||
goto close_clk;
|
||||
|
||||
/* perst assert Endpoint */
|
||||
if (!gpio_request(kirin_pcie->gpio_id_reset, "pcie_perst")) {
|
||||
usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
|
||||
ret = gpio_direction_output(kirin_pcie->gpio_id_reset, 1);
|
||||
if (ret)
|
||||
goto close_clk;
|
||||
usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
close_clk:
|
||||
kirin_pcie_clk_ctrl(kirin_pcie, false);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie,
|
||||
bool on)
|
||||
{
|
||||
@ -444,7 +501,7 @@ static int kirin_pcie_probe(struct platform_device *pdev)
|
||||
pci->pp.ops = &kirin_pcie_host_ops;
|
||||
kirin_pcie->pci = pci;
|
||||
|
||||
ret = kirin_pcie_get_clk(kirin_pcie, pdev);
|
||||
ret = hi3660_pcie_phy_init(pdev, kirin_pcie);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@ -452,16 +509,7 @@ static int kirin_pcie_probe(struct platform_device *pdev)
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
kirin_pcie->gpio_id_reset = of_get_named_gpio(dev->of_node,
|
||||
"reset-gpios", 0);
|
||||
if (kirin_pcie->gpio_id_reset == -EPROBE_DEFER) {
|
||||
return -EPROBE_DEFER;
|
||||
} else if (!gpio_is_valid(kirin_pcie->gpio_id_reset)) {
|
||||
dev_err(dev, "unable to get a valid gpio pin\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = kirin_pcie_power_on(kirin_pcie);
|
||||
ret = hi3660_pcie_phy_power_on(kirin_pcie);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@ -479,8 +527,8 @@ static struct platform_driver kirin_pcie_driver = {
|
||||
.probe = kirin_pcie_probe,
|
||||
.driver = {
|
||||
.name = "kirin-pcie",
|
||||
.of_match_table = kirin_pcie_match,
|
||||
.suppress_bind_attrs = true,
|
||||
.of_match_table = kirin_pcie_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(kirin_pcie_driver);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user