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Minimal updates to OMAP board-*.c files while converting

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things to device tree based booting.
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Merge tag 'omap-for-v3.9/board-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/boards

From Tony Lindgren:
Minimal updates to OMAP board-*.c files while converting
things to device tree based booting.

* tag 'omap-for-v3.9/board-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: omap2plus_defconfig: enable omap1 rtc
  RX-51: Register twl4030-madc device
  RX-51: Add leds lp5523 names from Maemo 5 2.6.28 kernel
  ARM: OMAP2+: AM33XX: omap2plus_defconfig: Add support for few drivers
  ARM: OMAP1: nokia770: enable CBUS/Retu
  ARM: OMAP2+: omap2plus_defconfig: enable CMA allocator
  ARM: OMAP2+: omap2plus_defconfig: enable TFP410 chip support
  ARM: OMAP3: igep0020: simplify GPIO LEDs dependencies
  ARM: OMAP2+: craneboard: support the TPS65910 PMU
  ARM: OMAP2+: craneboard: support NAND device
  ARM: OMAP3: cm-t3517: add MMC support
  ARM: OMAP2+: Remove apollon board support
  + Linux 3.8-rc6

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2013-02-05 14:06:09 -08:00
commit 61cfd87360
500 changed files with 4337 additions and 2792 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/device-mapper/dm-raid.txt
View File

@ -141,3 +141,4 @@ Version History
1.2.0 Handle creation of arrays that contain failed devices.
1.3.0 Added support for RAID 10
1.3.1 Allow device replacement/rebuild for RAID 10
1.3.2 Fix/improve redundancy checking for RAID10

5
Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
View File

@ -81,7 +81,8 @@ PA31 TXD4
Required properties for pin configuration node:
- atmel,pins: 4 integers array, represents a group of pins mux and config
setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
The PERIPH 0 means gpio.
The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B...
PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...
Bits used for CONFIG:
PULL_UP (1 << 0): indicate this pin need a pull up.
@ -126,7 +127,7 @@ pinctrl@fffff400 {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<1 14 0x1 0x0 /* PB14 periph A */
1 15 0x1 0x1>; /* PB15 periph with pullup */
1 15 0x1 0x1>; /* PB15 periph A with pullup */
};
};
};

18
Documentation/filesystems/f2fs.txt
View File

@ -175,9 +175,9 @@ consists of multiple segments as described below.
align with the zone size <-|
|-> align with the segment size
_________________________________________________________________________
| | | Node | Segment | Segment | |
| Superblock | Checkpoint | Address | Info. | Summary | Main |
| (SB) | (CP) | Table (NAT) | Table (SIT) | Area (SSA) | |
| | | Segment | Node | Segment | |
| Superblock | Checkpoint | Info. | Address | Summary | Main |
| (SB) | (CP) | Table (SIT) | Table (NAT) | Area (SSA) | |
|____________|_____2______|______N______|______N______|______N_____|__N___|
. .
. .
@ -200,14 +200,14 @@ consists of multiple segments as described below.
: It contains file system information, bitmaps for valid NAT/SIT sets, orphan
inode lists, and summary entries of current active segments.
- Node Address Table (NAT)
: It is composed of a block address table for all the node blocks stored in
Main area.
- Segment Information Table (SIT)
: It contains segment information such as valid block count and bitmap for the
validity of all the blocks.
- Node Address Table (NAT)
: It is composed of a block address table for all the node blocks stored in
Main area.
- Segment Summary Area (SSA)
: It contains summary entries which contains the owner information of all the
data and node blocks stored in Main area.
@ -236,13 +236,13 @@ For file system consistency, each CP points to which NAT and SIT copies are
valid, as shown as below.
+--------+----------+---------+
| CP | NAT | SIT |
| CP | SIT | NAT |
+--------+----------+---------+
. . . .
. . . .
. . . .
+-------+-------+--------+--------+--------+--------+
| CP #0 | CP #1 | NAT #0 | NAT #1 | SIT #0 | SIT #1 |
| CP #0 | CP #1 | SIT #0 | SIT #1 | NAT #0 | NAT #1 |
+-------+-------+--------+--------+--------+--------+
| ^ ^
| | |

0
Documentation/hid/hid-sensor.txt Executable file → Normal file
View File

27
Documentation/x86/boot.txt
View File

@ -57,6 +57,10 @@ Protocol 2.10: (Kernel 2.6.31) Added a protocol for relaxed alignment
Protocol 2.11: (Kernel 3.6) Added a field for offset of EFI handover
protocol entry point.
Protocol 2.12: (Kernel 3.9) Added the xloadflags field and extension fields
to struct boot_params for for loading bzImage and ramdisk
above 4G in 64bit.
**** MEMORY LAYOUT
The traditional memory map for the kernel loader, used for Image or
@ -182,7 +186,7 @@ Offset Proto Name Meaning
0230/4 2.05+ kernel_alignment Physical addr alignment required for kernel
0234/1 2.05+ relocatable_kernel Whether kernel is relocatable or not
0235/1 2.10+ min_alignment Minimum alignment, as a power of two
0236/2 N/A pad3 Unused
0236/2 2.12+ xloadflags Boot protocol option flags
0238/4 2.06+ cmdline_size Maximum size of the kernel command line
023C/4 2.07+ hardware_subarch Hardware subarchitecture
0240/8 2.07+ hardware_subarch_data Subarchitecture-specific data
@ -582,6 +586,27 @@ Protocol: 2.10+
misaligned kernel. Therefore, a loader should typically try each
power-of-two alignment from kernel_alignment down to this alignment.
Field name: xloadflags
Type: read
Offset/size: 0x236/2
Protocol: 2.12+
This field is a bitmask.
Bit 0 (read): XLF_KERNEL_64
- If 1, this kernel has the legacy 64-bit entry point at 0x200.
Bit 1 (read): XLF_CAN_BE_LOADED_ABOVE_4G
- If 1, kernel/boot_params/cmdline/ramdisk can be above 4G.
Bit 2 (read): XLF_EFI_HANDOVER_32
- If 1, the kernel supports the 32-bit EFI handoff entry point
given at handover_offset.
Bit 3 (read): XLF_EFI_HANDOVER_64
- If 1, the kernel supports the 64-bit EFI handoff entry point
given at handover_offset + 0x200.
Field name: cmdline_size
Type: read
Offset/size: 0x238/4

4
Documentation/x86/zero-page.txt
View File

@ -19,6 +19,9 @@ Offset Proto Name Meaning
090/010 ALL hd1_info hd1 disk parameter, OBSOLETE!!
0A0/010 ALL sys_desc_table System description table (struct sys_desc_table)
0B0/010 ALL olpc_ofw_header OLPC's OpenFirmware CIF and friends
0C0/004 ALL ext_ramdisk_image ramdisk_image high 32bits
0C4/004 ALL ext_ramdisk_size ramdisk_size high 32bits
0C8/004 ALL ext_cmd_line_ptr cmd_line_ptr high 32bits
140/080 ALL edid_info Video mode setup (struct edid_info)
1C0/020 ALL efi_info EFI 32 information (struct efi_info)
1E0/004 ALL alk_mem_k Alternative mem check, in KB
@ -27,6 +30,7 @@ Offset Proto Name Meaning
1E9/001 ALL eddbuf_entries Number of entries in eddbuf (below)
1EA/001 ALL edd_mbr_sig_buf_entries Number of entries in edd_mbr_sig_buffer
(below)
1EF/001 ALL sentinel Used to detect broken bootloaders
290/040 ALL edd_mbr_sig_buffer EDD MBR signatures
2D0/A00 ALL e820_map E820 memory map table
(array of struct e820entry)

10
MAINTAINERS
View File

@ -2966,7 +2966,7 @@ S: Maintained
F: drivers/net/ethernet/i825xx/eexpress.*
ETHERNET BRIDGE
M: Stephen Hemminger <shemminger@vyatta.com>
M: Stephen Hemminger <stephen@networkplumber.org>
L: bridge@lists.linux-foundation.org
L: netdev@vger.kernel.org
W: http://www.linuxfoundation.org/en/Net:Bridge
@ -4905,7 +4905,7 @@ S: Maintained
MARVELL GIGABIT ETHERNET DRIVERS (skge/sky2)
M: Mirko Lindner <mlindner@marvell.com>
M: Stephen Hemminger <shemminger@vyatta.com>
M: Stephen Hemminger <stephen@networkplumber.org>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/ethernet/marvell/sk*
@ -5180,7 +5180,7 @@ S: Supported
F: drivers/infiniband/hw/nes/
NETEM NETWORK EMULATOR
M: Stephen Hemminger <shemminger@vyatta.com>
M: Stephen Hemminger <stephen@networkplumber.org>
L: netem@lists.linux-foundation.org
S: Maintained
F: net/sched/sch_netem.c
@ -6585,7 +6585,7 @@ F: drivers/media/platform/s3c-camif/
F: include/media/s3c_camif.h
SERIAL DRIVERS
M: Alan Cox <alan@linux.intel.com>
M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
L: linux-serial@vger.kernel.org
S: Maintained
F: drivers/tty/serial
@ -7088,7 +7088,7 @@ F: include/uapi/sound/
F: sound/
SOUND - SOC LAYER / DYNAMIC AUDIO POWER MANAGEMENT (ASoC)
M: Liam Girdwood <lrg@ti.com>
M: Liam Girdwood <lgirdwood@gmail.com>
M: Mark Brown <broonie@opensource.wolfsonmicro.com>
T: git git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
L: alsa-devel@alsa-project.org (moderated for non-subscribers)

6
Makefile
View File

@ -1,8 +1,8 @@
VERSION = 3
PATCHLEVEL = 8
SUBLEVEL = 0
EXTRAVERSION = -rc4
NAME = Terrified Chipmunk
EXTRAVERSION = -rc6
NAME = Unicycling Gorilla
# *DOCUMENTATION*
# To see a list of typical targets execute "make help"
@ -169,7 +169,7 @@ SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \
-e s/arm.*/arm/ -e s/sa110/arm/ \
-e s/s390x/s390/ -e s/parisc64/parisc/ \
-e s/ppc.*/powerpc/ -e s/mips.*/mips/ \
-e s/sh[234].*/sh/ )
-e s/sh[234].*/sh/ -e s/aarch64.*/arm64/ )
# Cross compiling and selecting different set of gcc/bin-utils
# ---------------------------------------------------------------------------

2
arch/arm/boot/dts/armada-370-db.dts
View File

@ -26,7 +26,7 @@
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
reg = <0x00000000 0x40000000>; /* 1 GB */
};
soc {

14
arch/arm/boot/dts/armada-xp-mv78230.dtsi
View File

@ -50,27 +50,25 @@
};
gpio0: gpio@d0018100 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018100 0x40>,
<0xd0018800 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <16>, <17>, <18>, <19>;
interrupts = <82>, <83>, <84>, <85>;
};
gpio1: gpio@d0018140 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018140 0x40>,
<0xd0018840 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018140 0x40>;
ngpios = <17>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <20>, <21>, <22>;
interrupts = <87>, <88>, <89>;
};
};
};

21
arch/arm/boot/dts/armada-xp-mv78260.dtsi
View File

@ -51,39 +51,36 @@
};
gpio0: gpio@d0018100 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018100 0x40>,
<0xd0018800 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <16>, <17>, <18>, <19>;
interrupts = <82>, <83>, <84>, <85>;
};
gpio1: gpio@d0018140 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018140 0x40>,
<0xd0018840 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <20>, <21>, <22>, <23>;
interrupts = <87>, <88>, <89>, <90>;
};
gpio2: gpio@d0018180 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018180 0x40>,
<0xd0018870 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018180 0x40>;
ngpios = <3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <24>;
interrupts = <91>;
};
ethernet@d0034000 {

21
arch/arm/boot/dts/armada-xp-mv78460.dtsi
View File

@ -66,39 +66,36 @@
};
gpio0: gpio@d0018100 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018100 0x40>,
<0xd0018800 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <16>, <17>, <18>, <19>;
interrupts = <82>, <83>, <84>, <85>;
};
gpio1: gpio@d0018140 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018140 0x40>,
<0xd0018840 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <20>, <21>, <22>, <23>;
interrupts = <87>, <88>, <89>, <90>;
};
gpio2: gpio@d0018180 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018180 0x40>,
<0xd0018870 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018180 0x40>;
ngpios = <3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <24>;
interrupts = <91>;
};
ethernet@d0034000 {

4
arch/arm/boot/dts/at91rm9200.dtsi
View File

@ -336,8 +336,8 @@
i2c@0 {
compatible = "i2c-gpio";
gpios = <&pioA 23 0 /* sda */
&pioA 24 0 /* scl */
gpios = <&pioA 25 0 /* sda */
&pioA 26 0 /* scl */
>;
i2c-gpio,sda-open-drain;
i2c-gpio,scl-open-drain;

60
arch/arm/boot/dts/at91sam9x5.dtsi
View File

@ -143,6 +143,11 @@
atmel,pins =
<0 3 0x1 0x0>; /* PA3 periph A */
};
pinctrl_usart0_sck: usart0_sck-0 {
atmel,pins =
<0 4 0x1 0x0>; /* PA4 periph A */
};
};
usart1 {
@ -154,12 +159,17 @@
pinctrl_usart1_rts: usart1_rts-0 {
atmel,pins =
<3 27 0x3 0x0>; /* PC27 periph C */
<2 27 0x3 0x0>; /* PC27 periph C */
};
pinctrl_usart1_cts: usart1_cts-0 {
atmel,pins =
<3 28 0x3 0x0>; /* PC28 periph C */
<2 28 0x3 0x0>; /* PC28 periph C */
};
pinctrl_usart1_sck: usart1_sck-0 {
atmel,pins =
<2 28 0x3 0x0>; /* PC29 periph C */
};
};
@ -172,46 +182,56 @@
pinctrl_uart2_rts: uart2_rts-0 {
atmel,pins =
<0 0 0x2 0x0>; /* PB0 periph B */
<1 0 0x2 0x0>; /* PB0 periph B */
};
pinctrl_uart2_cts: uart2_cts-0 {
atmel,pins =
<0 1 0x2 0x0>; /* PB1 periph B */
<1 1 0x2 0x0>; /* PB1 periph B */
};
pinctrl_usart2_sck: usart2_sck-0 {
atmel,pins =
<1 2 0x2 0x0>; /* PB2 periph B */
};
};
usart3 {
pinctrl_uart3: usart3-0 {
atmel,pins =
<3 23 0x2 0x1 /* PC22 periph B with pullup */
3 23 0x2 0x0>; /* PC23 periph B */
<2 23 0x2 0x1 /* PC22 periph B with pullup */
2 23 0x2 0x0>; /* PC23 periph B */
};
pinctrl_usart3_rts: usart3_rts-0 {
atmel,pins =
<3 24 0x2 0x0>; /* PC24 periph B */
<2 24 0x2 0x0>; /* PC24 periph B */
};
pinctrl_usart3_cts: usart3_cts-0 {
atmel,pins =
<3 25 0x2 0x0>; /* PC25 periph B */
<2 25 0x2 0x0>; /* PC25 periph B */
};
pinctrl_usart3_sck: usart3_sck-0 {
atmel,pins =
<2 26 0x2 0x0>; /* PC26 periph B */
};
};
uart0 {
pinctrl_uart0: uart0-0 {
atmel,pins =
<3 8 0x3 0x0 /* PC8 periph C */
3 9 0x3 0x1>; /* PC9 periph C with pullup */
<2 8 0x3 0x0 /* PC8 periph C */
2 9 0x3 0x1>; /* PC9 periph C with pullup */
};
};
uart1 {
pinctrl_uart1: uart1-0 {
atmel,pins =
<3 16 0x3 0x0 /* PC16 periph C */
3 17 0x3 0x1>; /* PC17 periph C with pullup */
<2 16 0x3 0x0 /* PC16 periph C */
2 17 0x3 0x1>; /* PC17 periph C with pullup */
};
};
@ -240,14 +260,14 @@
pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
atmel,pins =
<1 8 0x1 0x0 /* PA8 periph A */
1 11 0x1 0x0 /* PA11 periph A */
1 12 0x1 0x0 /* PA12 periph A */
1 13 0x1 0x0 /* PA13 periph A */
1 14 0x1 0x0 /* PA14 periph A */
1 15 0x1 0x0 /* PA15 periph A */
1 16 0x1 0x0 /* PA16 periph A */
1 17 0x1 0x0>; /* PA17 periph A */
<1 8 0x1 0x0 /* PB8 periph A */
1 11 0x1 0x0 /* PB11 periph A */
1 12 0x1 0x0 /* PB12 periph A */
1 13 0x1 0x0 /* PB13 periph A */
1 14 0x1 0x0 /* PB14 periph A */
1 15 0x1 0x0 /* PB15 periph A */
1 16 0x1 0x0 /* PB16 periph A */
1 17 0x1 0x0>; /* PB17 periph A */
};
};

12
arch/arm/boot/dts/cros5250-common.dtsi
View File

@ -96,8 +96,8 @@
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3 3>;
samsung,dw-mshc-ddr-timing = <1 2 3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;
@ -120,8 +120,8 @@
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3 3>;
samsung,dw-mshc-ddr-timing = <1 2 3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;
@ -141,8 +141,8 @@
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3 3>;
samsung,dw-mshc-ddr-timing = <1 2 3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;

14
arch/arm/boot/dts/dove-cubox.dts
View File

@ -26,10 +26,15 @@
};
&uart0 { status = "okay"; };
&sdio0 { status = "okay"; };
&sata0 { status = "okay"; };
&i2c0 { status = "okay"; };
&sdio0 {
status = "okay";
/* sdio0 card detect is connected to wrong pin on CuBox */
cd-gpios = <&gpio0 12 1>;
};
&spi0 {
status = "okay";
@ -42,9 +47,14 @@
};
&pinctrl {
pinctrl-0 = <&pmx_gpio_18>;
pinctrl-0 = <&pmx_gpio_12 &pmx_gpio_18>;
pinctrl-names = "default";
pmx_gpio_12: pmx-gpio-12 {
marvell,pins = "mpp12";
marvell,function = "gpio";
};
pmx_gpio_18: pmx-gpio-18 {
marvell,pins = "mpp18";
marvell,function = "gpio";

8
arch/arm/boot/dts/exynos5250-smdk5250.dts
View File

@ -115,8 +115,8 @@
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3 3>;
samsung,dw-mshc-ddr-timing = <1 2 3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;
@ -139,8 +139,8 @@
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3 3>;
samsung,dw-mshc-ddr-timing = <1 2 3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;

16
arch/arm/boot/dts/kirkwood-ns2-common.dtsi
View File

@ -1,4 +1,5 @@
/include/ "kirkwood.dtsi"
/include/ "kirkwood-6281.dtsi"
/ {
chosen {
@ -6,6 +7,21 @@
};
ocp@f1000000 {
pinctrl: pinctrl@10000 {
pinctrl-0 = < &pmx_spi &pmx_twsi0 &pmx_uart0
&pmx_ns2_sata0 &pmx_ns2_sata1>;
pinctrl-names = "default";
pmx_ns2_sata0: pmx-ns2-sata0 {
marvell,pins = "mpp21";
marvell,function = "sata0";
};
pmx_ns2_sata1: pmx-ns2-sata1 {
marvell,pins = "mpp20";
marvell,function = "sata1";
};
};
serial@12000 {
clock-frequency = <166666667>;
status = "okay";

2
arch/arm/boot/dts/kirkwood.dtsi
View File

@ -36,6 +36,7 @@
reg = <0x10100 0x40>;
ngpios = <32>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <35>, <36>, <37>, <38>;
};
@ -46,6 +47,7 @@
reg = <0x10140 0x40>;
ngpios = <18>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <39>, <40>, <41>;
};

2
arch/arm/boot/dts/kizbox.dts
View File

@ -48,6 +48,8 @@
macb0: ethernet@fffc4000 {
phy-mode = "mii";
pinctrl-0 = <&pinctrl_macb_rmii
&pinctrl_macb_rmii_mii_alt>;
status = "okay";
};

6
arch/arm/boot/dts/sunxi.dtsi
View File

@ -60,19 +60,21 @@
};
uart0: uart@01c28000 {
compatible = "ns8250";
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <1>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24000000>;
status = "disabled";
};
uart1: uart@01c28400 {
compatible = "ns8250";
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <2>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24000000>;
status = "disabled";
};

2
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
View File

@ -45,7 +45,6 @@
reg = <1>;
};
/* A7s disabled till big.LITTLE patches are available...
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
@ -63,7 +62,6 @@
compatible = "arm,cortex-a7";
reg = <0x102>;
};
*/
};
memory@80000000 {

3
arch/arm/configs/at91_dt_defconfig
View File

@ -19,6 +19,7 @@ CONFIG_SOC_AT91SAM9260=y
CONFIG_SOC_AT91SAM9263=y
CONFIG_SOC_AT91SAM9G45=y
CONFIG_SOC_AT91SAM9X5=y
CONFIG_SOC_AT91SAM9N12=y
CONFIG_MACH_AT91SAM_DT=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
CONFIG_AT91_TIMER_HZ=128
@ -31,7 +32,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
CONFIG_KEXEC=y
CONFIG_AUTO_ZRELADDR=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set

25
arch/arm/configs/omap2plus_defconfig
View File

@ -52,6 +52,11 @@ CONFIG_IP_PNP_RARP=y
# CONFIG_INET_LRO is not set
# CONFIG_IPV6 is not set
CONFIG_NETFILTER=y
CONFIG_CAN=m
CONFIG_CAN_RAW=m
CONFIG_CAN_BCM=m
CONFIG_CAN_C_CAN=m
CONFIG_CAN_C_CAN_PLATFORM=m
CONFIG_BT=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_H4=y
@ -64,6 +69,7 @@ CONFIG_MAC80211=m
CONFIG_MAC80211_RC_PID=y
CONFIG_MAC80211_RC_DEFAULT_PID=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_CMA=y
CONFIG_CONNECTOR=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
@ -83,6 +89,9 @@ CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_SENSORS_LIS3LV02D=m
CONFIG_SENSORS_TSL2550=m
CONFIG_SENSORS_LIS3_I2C=m
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_MULTI_LUN=y
@ -108,6 +117,7 @@ CONFIG_USB_KC2190=y
CONFIG_INPUT_JOYDEV=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_MATRIX=m
CONFIG_KEYBOARD_TWL4030=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y
@ -131,14 +141,17 @@ CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_TWL4030=y
CONFIG_W1=y
CONFIG_POWER_SUPPLY=y
CONFIG_SENSORS_LM75=m
CONFIG_WATCHDOG=y
CONFIG_OMAP_WATCHDOG=y
CONFIG_TWL4030_WATCHDOG=y
CONFIG_MFD_TPS65217=y
CONFIG_MFD_TPS65910=y
CONFIG_REGULATOR_TWL4030=y
CONFIG_REGULATOR_TPS65023=y
CONFIG_REGULATOR_TPS6507X=y
CONFIG_REGULATOR_TPS65217=y
CONFIG_REGULATOR_TPS65910=y
CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_MODE_HELPERS=y
@ -150,6 +163,7 @@ CONFIG_OMAP2_DSS_SDI=y
CONFIG_OMAP2_DSS_DSI=y
CONFIG_FB_OMAP2=m
CONFIG_PANEL_GENERIC_DPI=m
CONFIG_PANEL_TFP410=m
CONFIG_PANEL_SHARP_LS037V7DW01=m
CONFIG_PANEL_NEC_NL8048HL11_01B=m
CONFIG_PANEL_TAAL=m
@ -196,9 +210,20 @@ CONFIG_MMC_UNSAFE_RESUME=y
CONFIG_SDIO_UART=y
CONFIG_MMC_OMAP=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_TWL92330=y
CONFIG_RTC_DRV_TWL4030=y
CONFIG_RTC_DRV_OMAP=y
CONFIG_DMADEVICES=y
CONFIG_DMA_OMAP=y
CONFIG_EXT2_FS=y

2
arch/arm/kernel/debug.S
View File

@ -100,12 +100,14 @@ ENTRY(printch)
b 1b
ENDPROC(printch)
#ifdef CONFIG_MMU
ENTRY(debug_ll_addr)
addruart r2, r3, ip
str r2, [r0]
str r3, [r1]
mov pc, lr
ENDPROC(debug_ll_addr)
#endif
#else

5
arch/arm/kernel/head.S
View File

@ -246,6 +246,7 @@ __create_page_tables:
/*
* Then map boot params address in r2 if specified.
* We map 2 sections in case the ATAGs/DTB crosses a section boundary.
*/
mov r0, r2, lsr #SECTION_SHIFT
movs r0, r0, lsl #SECTION_SHIFT
@ -253,6 +254,8 @@ __create_page_tables:
addne r3, r3, #PAGE_OFFSET
addne r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
orrne r6, r7, r0
strne r6, [r3], #1 << PMD_ORDER
addne r6, r6, #1 << SECTION_SHIFT
strne r6, [r3]
#ifdef CONFIG_DEBUG_LL
@ -331,7 +334,7 @@ ENTRY(secondary_startup)
* as it has already been validated by the primary processor.
*/
#ifdef CONFIG_ARM_VIRT_EXT
bl __hyp_stub_install
bl __hyp_stub_install_secondary
#endif
safe_svcmode_maskall r9

18
arch/arm/kernel/hyp-stub.S
View File

@ -99,7 +99,7 @@ ENTRY(__hyp_stub_install_secondary)
* immediately.
*/
compare_cpu_mode_with_primary r4, r5, r6, r7
bxne lr
movne pc, lr
/*
* Once we have given up on one CPU, we do not try to install the
@ -111,7 +111,7 @@ ENTRY(__hyp_stub_install_secondary)
*/
cmp r4, #HYP_MODE
bxne lr @ give up if the CPU is not in HYP mode
movne pc, lr @ give up if the CPU is not in HYP mode
/*
* Configure HSCTLR to set correct exception endianness/instruction set
@ -120,7 +120,8 @@ ENTRY(__hyp_stub_install_secondary)
* Eventually, CPU-specific code might be needed -- assume not for now
*
* This code relies on the "eret" instruction to synchronize the
* various coprocessor accesses.
* various coprocessor accesses. This is done when we switch to SVC
* (see safe_svcmode_maskall).
*/
@ Now install the hypervisor stub:
adr r7, __hyp_stub_vectors
@ -155,14 +156,7 @@ THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE
1:
#endif
bic r7, r4, #MODE_MASK
orr r7, r7, #SVC_MODE
THUMB( orr r7, r7, #PSR_T_BIT )
msr spsr_cxsf, r7 @ This is SPSR_hyp.
__MSR_ELR_HYP(14) @ msr elr_hyp, lr
__ERET @ return, switching to SVC mode
@ The boot CPU mode is left in r4.
bx lr @ The boot CPU mode is left in r4.
ENDPROC(__hyp_stub_install_secondary)
__hyp_stub_do_trap:
@ -200,7 +194,7 @@ ENDPROC(__hyp_get_vectors)
@ fall through
ENTRY(__hyp_set_vectors)
__HVC(0)
bx lr
mov pc, lr
ENDPROC(__hyp_set_vectors)
#ifndef ZIMAGE

2
arch/arm/mach-at91/setup.c
View File

@ -105,6 +105,8 @@ static void __init soc_detect(u32 dbgu_base)
switch (socid) {
case ARCH_ID_AT91RM9200:
at91_soc_initdata.type = AT91_SOC_RM9200;
if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_NONE)
at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
at91_boot_soc = at91rm9200_soc;
break;

1
arch/arm/mach-imx/Kconfig
View File

@ -851,6 +851,7 @@ config SOC_IMX6Q
select HAVE_CAN_FLEXCAN if CAN
select HAVE_IMX_GPC
select HAVE_IMX_MMDC
select HAVE_IMX_SRC
select HAVE_SMP
select MFD_SYSCON
select PINCTRL

6
arch/arm/mach-imx/clk-imx25.c
View File

@ -254,9 +254,9 @@ int __init mx25_clocks_init(void)
clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.2");
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
clk_register_clkdev(clk[usbotg_ahb], "ahb", "fsl-usb2-udc");
clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
clk_register_clkdev(clk[usbotg_ahb], "ahb", "imx-udc-mx27");
clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
clk_register_clkdev(clk[nfc_ipg_per], NULL, "imx25-nand.0");
/* i.mx25 has the i.mx35 type cspi */
clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");

6
arch/arm/mach-imx/clk-imx27.c
View File

@ -236,9 +236,9 @@ int __init mx27_clocks_init(unsigned long fref)
clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0");
clk_register_clkdev(clk[csi_ahb_gate], "ahb", "imx27-camera.0");
clk_register_clkdev(clk[per4_gate], "per", "imx27-camera.0");
clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "fsl-usb2-udc");
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "fsl-usb2-udc");
clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "imx-udc-mx27");
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "imx-udc-mx27");
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0");
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0");

6
arch/arm/mach-imx/clk-imx31.c
View File

@ -139,9 +139,9 @@ int __init mx31_clocks_init(unsigned long fref)
clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2");
clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2");
clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
clk_register_clkdev(clk[usb_div_post], "per", "fsl-usb2-udc");
clk_register_clkdev(clk[usb_gate], "ahb", "fsl-usb2-udc");
clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
clk_register_clkdev(clk[usb_div_post], "per", "imx-udc-mx27");
clk_register_clkdev(clk[usb_gate], "ahb", "imx-udc-mx27");
clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
/* i.mx31 has the i.mx21 type uart */
clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");

6
arch/arm/mach-imx/clk-imx35.c
View File

@ -251,9 +251,9 @@ int __init mx35_clocks_init()
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.2");
clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc");
clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
clk_register_clkdev(clk[usbotg_gate], "ahb", "imx-udc-mx27");
clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0");
clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");

6
arch/arm/mach-imx/clk-imx51-imx53.c
View File

@ -269,9 +269,9 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2");
clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2");
clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2");
clk_register_clkdev(clk[usboh3_per_gate], "per", "fsl-usb2-udc");
clk_register_clkdev(clk[usboh3_gate], "ipg", "fsl-usb2-udc");
clk_register_clkdev(clk[usboh3_gate], "ahb", "fsl-usb2-udc");
clk_register_clkdev(clk[usboh3_per_gate], "per", "imx-udc-mx51");
clk_register_clkdev(clk[usboh3_gate], "ipg", "imx-udc-mx51");
clk_register_clkdev(clk[usboh3_gate], "ahb", "imx-udc-mx51");
clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand");
clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");

3
arch/arm/mach-imx/clk-imx6q.c
View File

@ -436,6 +436,9 @@ int __init mx6q_clocks_init(void)
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_prepare_enable(clk[clks_init_on[i]]);
/* Set initial power mode */
imx6q_set_lpm(WAIT_CLOCKED);
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
base = of_iomap(np, 0);
WARN_ON(!base);

1
arch/arm/mach-imx/common.h
View File

@ -142,6 +142,7 @@ extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
extern void imx6q_clock_map_io(void);
extern void imx_cpu_die(unsigned int cpu);
extern int imx_cpu_kill(unsigned int cpu);
#ifdef CONFIG_PM
extern void imx6q_pm_init(void);

1
arch/arm/mach-imx/devices/devices-common.h
View File

@ -63,6 +63,7 @@ struct platform_device *__init imx_add_flexcan(
#include <linux/fsl_devices.h>
struct imx_fsl_usb2_udc_data {
const char *devid;
resource_size_t iobase;
resource_size_t irq;
};

15
arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
View File

@ -11,35 +11,36 @@
#include "../hardware.h"
#include "devices-common.h"
#define imx_fsl_usb2_udc_data_entry_single(soc) \
#define imx_fsl_usb2_udc_data_entry_single(soc, _devid) \
{ \
.devid = _devid, \
.iobase = soc ## _USB_OTG_BASE_ADDR, \
.irq = soc ## _INT_USB_OTG, \
}
#ifdef CONFIG_SOC_IMX25
const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst =
imx_fsl_usb2_udc_data_entry_single(MX25);
imx_fsl_usb2_udc_data_entry_single(MX25, "imx-udc-mx27");
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst =
imx_fsl_usb2_udc_data_entry_single(MX27);
imx_fsl_usb2_udc_data_entry_single(MX27, "imx-udc-mx27");
#endif /* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_SOC_IMX31
const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst =
imx_fsl_usb2_udc_data_entry_single(MX31);
imx_fsl_usb2_udc_data_entry_single(MX31, "imx-udc-mx27");
#endif /* ifdef CONFIG_SOC_IMX31 */
#ifdef CONFIG_SOC_IMX35
const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst =
imx_fsl_usb2_udc_data_entry_single(MX35);
imx_fsl_usb2_udc_data_entry_single(MX35, "imx-udc-mx27");
#endif /* ifdef CONFIG_SOC_IMX35 */
#ifdef CONFIG_SOC_IMX51
const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data __initconst =
imx_fsl_usb2_udc_data_entry_single(MX51);
imx_fsl_usb2_udc_data_entry_single(MX51, "imx-udc-mx51");
#endif
struct platform_device *__init imx_add_fsl_usb2_udc(
@ -57,7 +58,7 @@ struct platform_device *__init imx_add_fsl_usb2_udc(
.flags = IORESOURCE_IRQ,
},
};
return imx_add_platform_device_dmamask("fsl-usb2-udc", -1,
return imx_add_platform_device_dmamask(data->devid, -1,
res, ARRAY_SIZE(res),
pdata, sizeof(*pdata), DMA_BIT_MASK(32));
}

2
arch/arm/mach-imx/devices/platform-imx-fb.c
View File

@ -54,7 +54,7 @@ struct platform_device *__init imx_add_imx_fb(
.flags = IORESOURCE_IRQ,
},
};
return imx_add_platform_device_dmamask("imx-fb", 0,
return imx_add_platform_device_dmamask(data->devid, 0,
res, ARRAY_SIZE(res),
pdata, sizeof(*pdata), DMA_BIT_MASK(32));
}

12
arch/arm/mach-imx/hotplug.c
View File

@ -46,9 +46,11 @@ static inline void cpu_enter_lowpower(void)
void imx_cpu_die(unsigned int cpu)
{
cpu_enter_lowpower();
imx_enable_cpu(cpu, false);
/* spin here until hardware takes it down */
while (1)
;
cpu_do_idle();
}
int imx_cpu_kill(unsigned int cpu)
{
imx_enable_cpu(cpu, false);
return 1;
}

3
arch/arm/mach-imx/iram_alloc.c
View File

@ -22,8 +22,7 @@
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/genalloc.h>
#include "iram.h"
#include "linux/platform_data/imx-iram.h"
static unsigned long iram_phys_base;
static void __iomem *iram_virt_base;

1
arch/arm/mach-imx/platsmp.c
View File

@ -92,5 +92,6 @@ struct smp_operations imx_smp_ops __initdata = {
.smp_boot_secondary = imx_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = imx_cpu_die,
.cpu_kill = imx_cpu_kill,
#endif
};

1
arch/arm/mach-imx/pm-imx6q.c
View File

@ -41,6 +41,7 @@ static int imx6q_pm_enter(suspend_state_t state)
cpu_suspend(0, imx6q_suspend_finish);
imx_smp_prepare();
imx_gpc_post_resume();
imx6q_set_lpm(WAIT_CLOCKED);
break;
default:
return -EINVAL;

14
arch/arm/mach-integrator/pci_v3.c
View File

@ -475,13 +475,12 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
{
int ret = 0;
if (!ap_syscon_base)
return -EINVAL;
if (nr == 0) {
sys->mem_offset = PHYS_PCI_MEM_BASE;
ret = pci_v3_setup_resources(sys);
/* Remap the Integrator system controller */
ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
if (!ap_syscon_base)
return -EINVAL;
}
return ret;
@ -497,6 +496,13 @@ void __init pci_v3_preinit(void)
unsigned int temp;
int ret;
/* Remap the Integrator system controller */
ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
if (!ap_syscon_base) {
pr_err("unable to remap the AP syscon for PCIv3\n");
return;
}
pcibios_min_mem = 0x00100000;
/*

38
arch/arm/mach-kirkwood/board-ns2.c
View File

@ -18,47 +18,11 @@
#include <linux/gpio.h>
#include <linux/of.h>
#include "common.h"
#include "mpp.h"
static struct mv643xx_eth_platform_data ns2_ge00_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR(8),
};
static unsigned int ns2_mpp_config[] __initdata = {
MPP0_SPI_SCn,
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
MPP3_SPI_MISO,
MPP4_NF_IO6,
MPP5_NF_IO7,
MPP6_SYSRST_OUTn,
MPP7_GPO, /* Fan speed (bit 1) */
MPP8_TW0_SDA,
MPP9_TW0_SCK,
MPP10_UART0_TXD,
MPP11_UART0_RXD,
MPP12_GPO, /* Red led */
MPP14_GPIO, /* USB fuse */
MPP16_GPIO, /* SATA 0 power */
MPP17_GPIO, /* SATA 1 power */
MPP18_NF_IO0,
MPP19_NF_IO1,
MPP20_SATA1_ACTn,
MPP21_SATA0_ACTn,
MPP22_GPIO, /* Fan speed (bit 0) */
MPP23_GPIO, /* Fan power */
MPP24_GPIO, /* USB mode select */
MPP25_GPIO, /* Fan rotation fail */
MPP26_GPIO, /* USB device vbus */
MPP28_GPIO, /* USB enable host vbus */
MPP29_GPIO, /* Blue led (slow register) */
MPP30_GPIO, /* Blue led (command register) */
MPP31_GPIO, /* Board power off */
MPP32_GPIO, /* Power button (0 = Released, 1 = Pushed) */
MPP33_GPO, /* Fan speed (bit 2) */
0
};
#define NS2_GPIO_POWER_OFF 31
static void ns2_power_off(void)
@ -71,8 +35,6 @@ void __init ns2_init(void)
/*
* Basic setup. Needs to be called early.
*/
kirkwood_mpp_conf(ns2_mpp_config);
if (of_machine_is_compatible("lacie,netspace_lite_v2") ||
of_machine_is_compatible("lacie,netspace_mini_v2"))
ns2_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);

2
arch/arm/mach-mvebu/Makefile
View File

@ -1,6 +1,8 @@
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
-I$(srctree)/arch/arm/plat-orion/include
AFLAGS_coherency_ll.o := -Wa,-march=armv7-a
obj-y += system-controller.o
obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o coherency_ll.o pmsu.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o

43
arch/arm/mach-omap1/board-nokia770.c
View File

@ -7,6 +7,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/init.h>
@ -23,6 +24,8 @@
#include <linux/platform_data/keypad-omap.h>
#include <linux/platform_data/lcd-mipid.h>
#include <linux/platform_data/gpio-omap.h>
#include <linux/platform_data/i2c-cbus-gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -212,6 +215,45 @@ static inline void nokia770_mmc_init(void)
}
#endif
#if defined(CONFIG_I2C_CBUS_GPIO) || defined(CONFIG_I2C_CBUS_GPIO_MODULE)
static struct i2c_cbus_platform_data nokia770_cbus_data = {
.clk_gpio = OMAP_MPUIO(9),
.dat_gpio = OMAP_MPUIO(10),
.sel_gpio = OMAP_MPUIO(11),
};
static struct platform_device nokia770_cbus_device = {
.name = "i2c-cbus-gpio",
.id = 2,
.dev = {
.platform_data = &nokia770_cbus_data,
},
};
static struct i2c_board_info nokia770_i2c_board_info_2[] __initdata = {
{
I2C_BOARD_INFO("retu-mfd", 0x01),
},
};
static void __init nokia770_cbus_init(void)
{
const int retu_irq_gpio = 62;
if (gpio_request_one(retu_irq_gpio, GPIOF_IN, "Retu IRQ"))
return;
irq_set_irq_type(gpio_to_irq(retu_irq_gpio), IRQ_TYPE_EDGE_RISING);
nokia770_i2c_board_info_2[0].irq = gpio_to_irq(retu_irq_gpio);
i2c_register_board_info(2, nokia770_i2c_board_info_2,
ARRAY_SIZE(nokia770_i2c_board_info_2));
platform_device_register(&nokia770_cbus_device);
}
#else /* CONFIG_I2C_CBUS_GPIO */
static void __init nokia770_cbus_init(void)
{
}
#endif /* CONFIG_I2C_CBUS_GPIO */
static void __init omap_nokia770_init(void)
{
/* On Nokia 770, the SleepX signal is masked with an
@ -233,6 +275,7 @@ static void __init omap_nokia770_init(void)
mipid_dev_init();
omap1_usb_init(&nokia770_usb_config);
nokia770_mmc_init();
nokia770_cbus_init();
}
MACHINE_START(NOKIA770, "Nokia 770")

6
arch/arm/mach-omap2/Kconfig
View File

@ -165,12 +165,6 @@ config MACH_OMAP_H4
select OMAP_DEBUG_DEVICES
select OMAP_PACKAGE_ZAF
config MACH_OMAP_APOLLON
bool "OMAP 2420 Apollon board"
depends on SOC_OMAP2420
default y
select OMAP_PACKAGE_ZAC
config MACH_OMAP_2430SDP
bool "OMAP 2430 SDP board"
depends on SOC_OMAP2430

1
arch/arm/mach-omap2/Makefile
View File

@ -220,7 +220,6 @@ endif
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o
obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o
obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o
obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o
obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o

59
arch/arm/mach-omap2/board-am3517crane.c
View File

@ -20,12 +20,18 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/mfd/tps65910.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "common.h"
#include "common-board-devices.h"
#include "board-flash.h"
#include "am35xx-emac.h"
#include "mux.h"
@ -36,6 +42,7 @@
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#endif
@ -51,6 +58,54 @@ static struct usbhs_omap_board_data usbhs_bdata __initdata = {
.reset_gpio_port[2] = -EINVAL
};
static struct mtd_partition crane_nand_partitions[] = {
{
.name = "X-Loader",
.offset = 0,
.size = 4 * NAND_BLOCK_SIZE,
.mask_flags = MTD_WRITEABLE,
},
{
.name = "U-Boot",
.offset = MTDPART_OFS_APPEND,
.size = 14 * NAND_BLOCK_SIZE,
.mask_flags = MTD_WRITEABLE,
},
{
.name = "U-Boot Env",
.offset = MTDPART_OFS_APPEND,
.size = 2 * NAND_BLOCK_SIZE,
},
{
.name = "Kernel",
.offset = MTDPART_OFS_APPEND,
.size = 40 * NAND_BLOCK_SIZE,
},
{
.name = "File System",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct tps65910_board tps65910_pdata = {
.irq = 7 + OMAP_INTC_START,
.en_ck32k_xtal = true,
};
static struct i2c_board_info __initdata tps65910_board_info[] = {
{
I2C_BOARD_INFO("tps65910", 0x2d),
.platform_data = &tps65910_pdata,
},
};
static void __init am3517_crane_i2c_init(void)
{
omap_register_i2c_bus(1, 2600, tps65910_board_info,
ARRAY_SIZE(tps65910_board_info));
}
static void __init am3517_crane_init(void)
{
int ret;
@ -58,6 +113,10 @@ static void __init am3517_crane_init(void)
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_serial_init();
omap_sdrc_init(NULL, NULL);
board_nand_init(crane_nand_partitions,
ARRAY_SIZE(crane_nand_partitions), 0,
NAND_BUSWIDTH_16, NULL);
am3517_crane_i2c_init();
/* Configure GPIO for EHCI port */
if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) {

342
arch/arm/mach-omap2/board-apollon.c
View File

@ -1,342 +0,0 @@
/*
* linux/arch/arm/mach-omap2/board-apollon.c
*
* Copyright (C) 2005,2006 Samsung Electronics
* Author: Kyungmin Park <kyungmin.park@samsung.com>
*
* Modified from mach-omap/omap2/board-h4.c
*
* Code for apollon OMAP2 board. Should work on many OMAP2 systems where
* the bootloader passes the board-specific data to the kernel.
* Do not put any board specific code to this file; create a new machine
* type if you need custom low-level initializations.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/onenand.h>
#include <linux/delay.h>
#include <linux/leds.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/smc91x.h>
#include <linux/gpio.h>
#include <linux/platform_data/leds-omap.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include "common.h"
#include "gpmc.h"
#include <video/omapdss.h>
#include <video/omap-panel-generic-dpi.h>
#include "mux.h"
#include "control.h"
/* LED & Switch macros */
#define LED0_GPIO13 13
#define LED1_GPIO14 14
#define LED2_GPIO15 15
#define SW_ENTER_GPIO16 16
#define SW_UP_GPIO17 17
#define SW_DOWN_GPIO58 58
#define APOLLON_FLASH_CS 0
#define APOLLON_ETH_CS 1
#define APOLLON_ETHR_GPIO_IRQ 74
static struct mtd_partition apollon_partitions[] = {
{
.name = "X-Loader + U-Boot",
.offset = 0,
.size = SZ_128K,
.mask_flags = MTD_WRITEABLE,
},
{
.name = "params",
.offset = MTDPART_OFS_APPEND,
.size = SZ_128K,
},
{
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = SZ_2M,
},
{
.name = "rootfs",
.offset = MTDPART_OFS_APPEND,
.size = SZ_16M,
},
{
.name = "filesystem00",
.offset = MTDPART_OFS_APPEND,
.size = SZ_32M,
},
{
.name = "filesystem01",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct onenand_platform_data apollon_flash_data = {
.parts = apollon_partitions,
.nr_parts = ARRAY_SIZE(apollon_partitions),
};
static struct resource apollon_flash_resource[] = {
[0] = {
.flags = IORESOURCE_MEM,
},
};
static struct platform_device apollon_onenand_device = {
.name = "onenand-flash",
.id = -1,
.dev = {
.platform_data = &apollon_flash_data,
},
.num_resources = ARRAY_SIZE(apollon_flash_resource),
.resource = apollon_flash_resource,
};
static void __init apollon_flash_init(void)
{
unsigned long base;
if (gpmc_cs_request(APOLLON_FLASH_CS, SZ_128K, &base) < 0) {
printk(KERN_ERR "Cannot request OneNAND GPMC CS\n");
return;
}
apollon_flash_resource[0].start = base;
apollon_flash_resource[0].end = base + SZ_128K - 1;
}
static struct smc91x_platdata appolon_smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource apollon_smc91x_resources[] = {
[0] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
},
};
static struct platform_device apollon_smc91x_device = {
.name = "smc91x",
.id = -1,
.dev = {
.platform_data = &appolon_smc91x_info,
},
.num_resources = ARRAY_SIZE(apollon_smc91x_resources),
.resource = apollon_smc91x_resources,
};
static struct omap_led_config apollon_led_config[] = {
{
.cdev = {
.name = "apollon:led0",
},
.gpio = LED0_GPIO13,
},
{
.cdev = {
.name = "apollon:led1",
},
.gpio = LED1_GPIO14,
},
{
.cdev = {
.name = "apollon:led2",
},
.gpio = LED2_GPIO15,
},
};
static struct omap_led_platform_data apollon_led_data = {
.nr_leds = ARRAY_SIZE(apollon_led_config),
.leds = apollon_led_config,
};
static struct platform_device apollon_led_device = {
.name = "omap-led",
.id = -1,
.dev = {
.platform_data = &apollon_led_data,
},
};
static struct platform_device *apollon_devices[] __initdata = {
&apollon_onenand_device,
&apollon_smc91x_device,
&apollon_led_device,
};
static inline void __init apollon_init_smc91x(void)
{
unsigned long base;
unsigned int rate;
struct clk *gpmc_fck;
int eth_cs;
int err;
gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
if (IS_ERR(gpmc_fck)) {
WARN_ON(1);
return;
}
clk_prepare_enable(gpmc_fck);
rate = clk_get_rate(gpmc_fck);
eth_cs = APOLLON_ETH_CS;
/* Make sure CS1 timings are correct */
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);
if (rate >= 160000000) {
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
} else if (rate >= 130000000) {
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
} else {/* rate = 100000000 */
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
}
if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) {
printk(KERN_ERR "Failed to request GPMC CS for smc91x\n");
goto out;
}
apollon_smc91x_resources[0].start = base + 0x300;
apollon_smc91x_resources[0].end = base + 0x30f;
udelay(100);
omap_mux_init_gpio(APOLLON_ETHR_GPIO_IRQ, 0);
err = gpio_request_one(APOLLON_ETHR_GPIO_IRQ, GPIOF_IN, "SMC91x irq");
if (err) {
printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
APOLLON_ETHR_GPIO_IRQ);
gpmc_cs_free(APOLLON_ETH_CS);
}
out:
clk_disable_unprepare(gpmc_fck);
clk_put(gpmc_fck);
}
static struct panel_generic_dpi_data apollon_panel_data = {
.name = "apollon",
};
static struct omap_dss_device apollon_lcd_device = {
.name = "lcd",
.driver_name = "generic_dpi_panel",
.type = OMAP_DISPLAY_TYPE_DPI,
.phy.dpi.data_lines = 18,
.data = &apollon_panel_data,
};
static struct omap_dss_device *apollon_dss_devices[] = {
&apollon_lcd_device,
};
static struct omap_dss_board_info apollon_dss_data = {
.num_devices = ARRAY_SIZE(apollon_dss_devices),
.devices = apollon_dss_devices,
.default_device = &apollon_lcd_device,
};
static struct gpio apollon_gpio_leds[] __initdata = {
{ LED0_GPIO13, GPIOF_OUT_INIT_LOW, "LED0" }, /* LED0 - AA10 */
{ LED1_GPIO14, GPIOF_OUT_INIT_LOW, "LED1" }, /* LED1 - AA6 */
{ LED2_GPIO15, GPIOF_OUT_INIT_LOW, "LED2" }, /* LED2 - AA4 */
};
static void __init apollon_led_init(void)
{
omap_mux_init_signal("vlynq_clk.gpio_13", 0);
omap_mux_init_signal("vlynq_rx1.gpio_14", 0);
omap_mux_init_signal("vlynq_rx0.gpio_15", 0);
gpio_request_array(apollon_gpio_leds, ARRAY_SIZE(apollon_gpio_leds));
}
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#endif
static void __init omap_apollon_init(void)
{
u32 v;
omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
apollon_init_smc91x();
apollon_led_init();
apollon_flash_init();
/* REVISIT: where's the correct place */
omap_mux_init_signal("sys_nirq", OMAP_PULL_ENA | OMAP_PULL_UP);
/* LCD PWR_EN */
omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP);
/* Use Internal loop-back in MMC/SDIO Module Input Clock selection */
v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
v |= (1 << 24);
omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
/*
* Make sure the serial ports are muxed on at this point.
* You have to mux them off in device drivers later on
* if not needed.
*/
apollon_smc91x_resources[1].start = gpio_to_irq(APOLLON_ETHR_GPIO_IRQ);
apollon_smc91x_resources[1].end = gpio_to_irq(APOLLON_ETHR_GPIO_IRQ);
platform_add_devices(apollon_devices, ARRAY_SIZE(apollon_devices));
omap_serial_init();
omap_sdrc_init(NULL, NULL);
omap_display_init(&apollon_dss_data);
}
MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
/* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
.atag_offset = 0x100,
.reserve = omap_reserve,
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_irq = omap2_init_irq,
.handle_irq = omap2_intc_handle_irq,
.init_machine = omap_apollon_init,
.init_late = omap2420_init_late,
.timer = &omap2_timer,
.restart = omap2xxx_restart,
MACHINE_END

27
arch/arm/mach-omap2/board-cm-t3517.c
View File

@ -32,6 +32,7 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/mmc/host.h>
#include <linux/can/platform/ti_hecc.h>
#include <asm/mach-types.h>
@ -46,6 +47,7 @@
#include "mux.h"
#include "control.h"
#include "hsmmc.h"
#include "common-board-devices.h"
#include "am35xx-emac.h"
#include "gpmc-nand.h"
@ -121,6 +123,26 @@ static void cm_t3517_init_hecc(void)
static inline void cm_t3517_init_hecc(void) {}
#endif
#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
static struct omap2_hsmmc_info cm_t3517_mmc[] = {
{
.mmc = 1,
.caps = MMC_CAP_4_BIT_DATA,
.gpio_cd = 144,
.gpio_wp = 59,
},
{
.mmc = 2,
.caps = MMC_CAP_4_BIT_DATA,
.gpio_cd = -EINVAL,
.gpio_wp = -EINVAL,
},
{} /* Terminator */
};
#else
#define cm_t3517_mmc NULL
#endif
#if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE)
#define RTC_IO_GPIO (153)
#define RTC_WR_GPIO (154)
@ -271,6 +293,10 @@ static struct omap_board_mux board_mux[] __initdata = {
/* CM-T3517 USB HUB nRESET */
OMAP3_MUX(MCBSP4_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
/* CD - GPIO144 and WP - GPIO59 for MMC1 - SB-T35 */
OMAP3_MUX(UART2_CTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
OMAP3_MUX(GPMC_CLK, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#endif
@ -286,6 +312,7 @@ static void __init cm_t3517_init(void)
cm_t3517_init_usbh();
cm_t3517_init_hecc();
am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1);
omap_hsmmc_init(cm_t3517_mmc);
}
MACHINE_START(CM_T3517, "Compulab CM-T3517")

16
arch/arm/mach-omap2/board-igep0020.c
View File

@ -300,20 +300,20 @@ static struct omap2_hsmmc_info mmc[] = {
static struct gpio_led igep_gpio_leds[] = {
[0] = {
.name = "gpio-led:red:d0",
.default_trigger = "default-off"
.name = "omap3:red:user0",
.default_state = 0,
},
[1] = {
.name = "gpio-led:green:d0",
.default_trigger = "default-off",
.name = "omap3:green:boot",
.default_state = 1,
},
[2] = {
.name = "gpio-led:red:d1",
.default_trigger = "default-off",
.name = "omap3:red:user1",
.default_state = 0,
},
[3] = {
.name = "gpio-led:green:d1",
.default_trigger = "heartbeat",
.name = "omap3:green:user1",
.default_state = 0,
.gpio = -EINVAL, /* gets replaced */
.active_low = 1,
},

6
arch/arm/mach-omap2/board-omap4panda.c
View File

@ -397,6 +397,12 @@ static struct omap_board_mux board_mux[] __initdata = {
OMAP_PULL_ENA),
OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
/* UART2 - BT/FM/GPS shared transport */
OMAP4_MUX(UART2_CTS, OMAP_PIN_INPUT | OMAP_MUX_MODE0),
OMAP4_MUX(UART2_RTS, OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
OMAP4_MUX(UART2_RX, OMAP_PIN_INPUT | OMAP_MUX_MODE0),
OMAP4_MUX(UART2_TX, OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};

20
arch/arm/mach-omap2/board-rx51-peripherals.c
View File

@ -162,30 +162,39 @@ static struct tsl2563_platform_data rx51_tsl2563_platform_data = {
#if defined(CONFIG_LEDS_LP5523) || defined(CONFIG_LEDS_LP5523_MODULE)
static struct lp5523_led_config rx51_lp5523_led_config[] = {
{
.name = "lp5523:kb1",
.chan_nr = 0,
.led_current = 50,
}, {
.name = "lp5523:kb2",
.chan_nr = 1,
.led_current = 50,
}, {
.name = "lp5523:kb3",
.chan_nr = 2,
.led_current = 50,
}, {
.name = "lp5523:kb4",
.chan_nr = 3,
.led_current = 50,
}, {
.name = "lp5523:b",
.chan_nr = 4,
.led_current = 50,
}, {
.name = "lp5523:g",
.chan_nr = 5,
.led_current = 50,
}, {
.name = "lp5523:r",
.chan_nr = 6,
.led_current = 50,
}, {
.name = "lp5523:kb5",
.chan_nr = 7,
.led_current = 50,
}, {
.name = "lp5523:kb6",
.chan_nr = 8,
.led_current = 50,
}
@ -1253,6 +1262,16 @@ static void __init rx51_init_lirc(void)
}
#endif
static struct platform_device madc_hwmon = {
.name = "twl4030_madc_hwmon",
.id = -1,
};
static void __init rx51_init_twl4030_hwmon(void)
{
platform_device_register(&madc_hwmon);
}
void __init rx51_peripherals_init(void)
{
rx51_i2c_init();
@ -1272,5 +1291,6 @@ void __init rx51_peripherals_init(void)
omap_hsmmc_init(mmc);
rx51_charger_init();
rx51_init_twl4030_hwmon();
}

2
arch/arm/mach-omap2/cclock2420_data.c
View File

@ -1935,6 +1935,8 @@ int __init omap2420_clk_init(void)
omap2_init_clk_hw_omap_clocks(c->lk.clk);
}
omap2xxx_clkt_vps_late_init();
omap2_clk_disable_autoidle_all();
omap2_clk_enable_init_clocks(enable_init_clks,

2
arch/arm/mach-omap2/cclock2430_data.c
View File

@ -2050,6 +2050,8 @@ int __init omap2430_clk_init(void)
omap2_init_clk_hw_omap_clocks(c->lk.clk);
}
omap2xxx_clkt_vps_late_init();
omap2_clk_disable_autoidle_all();
omap2_clk_enable_init_clocks(enable_init_clks,

3
arch/arm/mach-omap2/cclock44xx_data.c
View File

@ -2026,14 +2026,13 @@ int __init omap4xxx_clk_init(void)
* On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
* state when turning the ABE clock domain. Workaround this by
* locking the ABE DPLL on boot.
* Lock the ABE DPLL in any case to avoid issues with audio.
*/
if (cpu_is_omap446x()) {
rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck);
if (!rc)
rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ);
if (rc)
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
}
return 0;
}

2
arch/arm/mach-omap2/devices.c
View File

@ -639,7 +639,7 @@ static int count_ocp2scp_devices(struct omap_ocp2scp_dev *ocp2scp_dev)
return cnt;
}
static void omap_init_ocp2scp(void)
static void __init omap_init_ocp2scp(void)
{
struct omap_hwmod *oh;
struct platform_device *pdev;

3
arch/arm/mach-omap2/drm.c
View File

@ -25,6 +25,7 @@
#include <linux/dma-mapping.h>
#include <linux/platform_data/omap_drm.h>
#include "soc.h"
#include "omap_device.h"
#include "omap_hwmod.h"
@ -56,7 +57,7 @@ static int __init omap_init_drm(void)
oh->name);
}
platform_data.omaprev = GET_OMAP_REVISION();
platform_data.omaprev = GET_OMAP_TYPE;
return platform_device_register(&omap_drm_device);

3
arch/arm/mach-omap2/gpmc.c
View File

@ -783,9 +783,6 @@ static int gpmc_mem_init(void)
* even if we didn't boot from ROM.
*/
boot_rom_space = BOOT_ROM_SPACE;
/* In apollon the CS0 is mapped as 0x0000 0000 */
if (machine_is_omap_apollon())
boot_rom_space = 0;
gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
gpmc_mem_root.end = GPMC_MEM_END;

6
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View File

@ -2132,8 +2132,12 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
* currently reset very early during boot, before I2C is
* available, so it doesn't seem that we have any choice in
* the kernel other than to avoid resetting it.
*
* Also, McPDM needs to be configured to NO_IDLE mode when it
* is in used otherwise vital clocks will be gated which
* results 'slow motion' audio playback.
*/
.flags = HWMOD_EXT_OPT_MAIN_CLK,
.flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
.mpu_irqs = omap44xx_mcpdm_irqs,
.sdma_reqs = omap44xx_mcpdm_sdma_reqs,
.main_clk = "mcpdm_fck",

8
arch/arm/mach-omap2/timer.c
View File

@ -165,15 +165,11 @@ static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
struct device_node *np;
for_each_matching_node(np, match) {
if (!of_device_is_available(np)) {
of_node_put(np);
if (!of_device_is_available(np))
continue;
}
if (property && !of_get_property(np, property, NULL)) {
of_node_put(np);
if (property && !of_get_property(np, property, NULL))
continue;
}
of_add_property(np, &device_disabled);
return np;

2
arch/arm/mach-s3c64xx/mach-crag6410-module.c
View File

@ -47,7 +47,7 @@ static struct spi_board_info wm1253_devs[] = {
.bus_num = 0,
.chip_select = 0,
.mode = SPI_MODE_0,
.irq = S3C_EINT(5),
.irq = S3C_EINT(4),
.controller_data = &wm0010_spi_csinfo,
.platform_data = &wm0010_pdata,
},

2
arch/arm/mach-s3c64xx/pm.c
View File

@ -338,8 +338,10 @@ int __init s3c64xx_pm_init(void)
for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++)
pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false);
#ifdef CONFIG_S3C_DEV_FB
if (dev_get_platdata(&s3c_device_fb.dev))
pm_genpd_add_device(&s3c64xx_pm_f.pd, &s3c_device_fb.dev);
#endif
return 0;
}

18
arch/arm/mm/dma-mapping.c
View File

@ -774,25 +774,27 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset,
size_t size, enum dma_data_direction dir,
void (*op)(const void *, size_t, int))
{
unsigned long pfn;
size_t left = size;
pfn = page_to_pfn(page) + offset / PAGE_SIZE;
offset %= PAGE_SIZE;
/*
* A single sg entry may refer to multiple physically contiguous
* pages. But we still need to process highmem pages individually.
* If highmem is not configured then the bulk of this loop gets
* optimized out.
*/
size_t left = size;
do {
size_t len = left;
void *vaddr;
page = pfn_to_page(pfn);
if (PageHighMem(page)) {
if (len + offset > PAGE_SIZE) {
if (offset >= PAGE_SIZE) {
page += offset / PAGE_SIZE;
offset %= PAGE_SIZE;
}
if (len + offset > PAGE_SIZE)
len = PAGE_SIZE - offset;
}
vaddr = kmap_high_get(page);
if (vaddr) {
vaddr += offset;
@ -809,7 +811,7 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset,
op(vaddr, len, dir);
}
offset = 0;
page++;
pfn++;
left -= len;
} while (left);
}

2
arch/arm/mm/mmu.c
View File

@ -283,7 +283,7 @@ static struct mem_type mem_types[] = {
},
[MT_MEMORY_SO] = {
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
L_PTE_MT_UNCACHED,
L_PTE_MT_UNCACHED | L_PTE_XN,
.prot_l1 = PMD_TYPE_TABLE,
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
PMD_SECT_UNCACHED | PMD_SECT_XN,

2
arch/arm/plat-versatile/headsmp.S
View File

@ -20,7 +20,7 @@
*/
ENTRY(versatile_secondary_startup)
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15
bic r0, #0xff000000
adr r4, 1f
ldmia r4, {r5, r6}
sub r4, r4, r5

6
arch/arm/vfp/entry.S
View File

@ -22,7 +22,7 @@
@ IRQs disabled.
@
ENTRY(do_vfp)
#ifdef CONFIG_PREEMPT
#ifdef CONFIG_PREEMPT_COUNT
ldr r4, [r10, #TI_PREEMPT] @ get preempt count
add r11, r4, #1 @ increment it
str r11, [r10, #TI_PREEMPT]
@ -35,7 +35,7 @@ ENTRY(do_vfp)
ENDPROC(do_vfp)
ENTRY(vfp_null_entry)
#ifdef CONFIG_PREEMPT
#ifdef CONFIG_PREEMPT_COUNT
get_thread_info r10
ldr r4, [r10, #TI_PREEMPT] @ get preempt count
sub r11, r4, #1 @ decrement it
@ -53,7 +53,7 @@ ENDPROC(vfp_null_entry)
__INIT
ENTRY(vfp_testing_entry)
#ifdef CONFIG_PREEMPT
#ifdef CONFIG_PREEMPT_COUNT
get_thread_info r10
ldr r4, [r10, #TI_PREEMPT] @ get preempt count
sub r11, r4, #1 @ decrement it

4
arch/arm/vfp/vfphw.S
View File

@ -168,7 +168,7 @@ vfp_hw_state_valid:
@ else it's one 32-bit instruction, so
@ always subtract 4 from the following
@ instruction address.
#ifdef CONFIG_PREEMPT
#ifdef CONFIG_PREEMPT_COUNT
get_thread_info r10
ldr r4, [r10, #TI_PREEMPT] @ get preempt count
sub r11, r4, #1 @ decrement it
@ -192,7 +192,7 @@ look_for_VFP_exceptions:
@ not recognised by VFP
DBGSTR "not VFP"
#ifdef CONFIG_PREEMPT
#ifdef CONFIG_PREEMPT_COUNT
get_thread_info r10
ldr r4, [r10, #TI_PREEMPT] @ get preempt count
sub r11, r4, #1 @ decrement it

5
arch/arm64/include/asm/elf.h
View File

@ -26,7 +26,10 @@
typedef unsigned long elf_greg_t;
#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
#define ELF_NGREG (sizeof(struct user_pt_regs) / sizeof(elf_greg_t))
#define ELF_CORE_COPY_REGS(dest, regs) \
*(struct user_pt_regs *)&(dest) = (regs)->user_regs;
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
typedef struct user_fpsimd_state elf_fpregset_t;

27
arch/ia64/kernel/ptrace.c
View File

@ -672,33 +672,6 @@ ptrace_attach_sync_user_rbs (struct task_struct *child)
read_unlock(&tasklist_lock);
}
static inline int
thread_matches (struct task_struct *thread, unsigned long addr)
{
unsigned long thread_rbs_end;
struct pt_regs *thread_regs;
if (ptrace_check_attach(thread, 0) < 0)
/*
* If the thread is not in an attachable state, we'll
* ignore it. The net effect is that if ADDR happens
* to overlap with the portion of the thread's
* register backing store that is currently residing
* on the thread's kernel stack, then ptrace() may end
* up accessing a stale value. But if the thread
* isn't stopped, that's a problem anyhow, so we're
* doing as well as we can...
*/
return 0;
thread_regs = task_pt_regs(thread);
thread_rbs_end = ia64_get_user_rbs_end(thread, thread_regs, NULL);
if (!on_kernel_rbs(addr, thread_regs->ar_bspstore, thread_rbs_end))
return 0;
return 1; /* looks like we've got a winner */
}
/*
* Write f32-f127 back to task->thread.fph if it has been modified.
*/

16
arch/m68k/include/asm/dma-mapping.h
View File

@ -21,6 +21,22 @@ extern void *dma_alloc_coherent(struct device *, size_t,
extern void dma_free_coherent(struct device *, size_t,
void *, dma_addr_t);
static inline void *dma_alloc_attrs(struct device *dev, size_t size,
dma_addr_t *dma_handle, gfp_t flag,
struct dma_attrs *attrs)
{
/* attrs is not supported and ignored */
return dma_alloc_coherent(dev, size, dma_handle, flag);
}
static inline void dma_free_attrs(struct device *dev, size_t size,
void *cpu_addr, dma_addr_t dma_handle,
struct dma_attrs *attrs)
{
/* attrs is not supported and ignored */
dma_free_coherent(dev, size, cpu_addr, dma_handle);
}
static inline void *dma_alloc_noncoherent(struct device *dev, size_t size,
dma_addr_t *handle, gfp_t flag)
{

2
arch/m68k/include/asm/pgtable_no.h
View File

@ -64,6 +64,8 @@ extern unsigned int kobjsize(const void *objp);
*/
#define VMALLOC_START 0
#define VMALLOC_END 0xffffffff
#define KMAP_START 0
#define KMAP_END 0xffffffff
#include <asm-generic/pgtable.h>

2
arch/m68k/include/asm/unistd.h
View File

@ -4,7 +4,7 @@
#include <uapi/asm/unistd.h>
#define NR_syscalls 348
#define NR_syscalls 349
#define __ARCH_WANT_OLD_READDIR
#define __ARCH_WANT_OLD_STAT

1
arch/m68k/include/uapi/asm/unistd.h
View File

@ -353,5 +353,6 @@
#define __NR_process_vm_readv 345
#define __NR_process_vm_writev 346
#define __NR_kcmp 347
#define __NR_finit_module 348
#endif /* _UAPI_ASM_M68K_UNISTD_H_ */

1
arch/m68k/kernel/syscalltable.S
View File

@ -368,4 +368,5 @@ ENTRY(sys_call_table)
.long sys_process_vm_readv /* 345 */
.long sys_process_vm_writev
.long sys_kcmp
.long sys_finit_module

8
arch/m68k/mm/init.c
View File

@ -39,6 +39,11 @@
void *empty_zero_page;
EXPORT_SYMBOL(empty_zero_page);
#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
extern void init_pointer_table(unsigned long ptable);
extern pmd_t *zero_pgtable;
#endif
#ifdef CONFIG_MMU
pg_data_t pg_data_map[MAX_NUMNODES];
@ -69,9 +74,6 @@ void __init m68k_setup_node(int node)
node_set_online(node);
}
extern void init_pointer_table(unsigned long ptable);
extern pmd_t *zero_pgtable;
#else /* CONFIG_MMU */
/*

3
arch/mips/bcm47xx/Kconfig
View File

@ -8,8 +8,10 @@ config BCM47XX_SSB
select SSB_DRIVER_EXTIF
select SSB_EMBEDDED
select SSB_B43_PCI_BRIDGE if PCI
select SSB_DRIVER_PCICORE if PCI
select SSB_PCICORE_HOSTMODE if PCI
select SSB_DRIVER_GPIO
select GPIOLIB
default y
help
Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support.
@ -25,6 +27,7 @@ config BCM47XX_BCMA
select BCMA_HOST_PCI if PCI
select BCMA_DRIVER_PCI_HOSTMODE if PCI
select BCMA_DRIVER_GPIO
select GPIOLIB
default y
help
Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus.

9
arch/mips/cavium-octeon/executive/cvmx-l2c.c
View File

@ -30,6 +30,7 @@
* measurement, and debugging facilities.
*/
#include <linux/compiler.h>
#include <linux/irqflags.h>
#include <asm/octeon/cvmx.h>
#include <asm/octeon/cvmx-l2c.h>
@ -285,22 +286,22 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter)
*/
static void fault_in(uint64_t addr, int len)
{
volatile char *ptr;
volatile char dummy;
char *ptr;
/*
* Adjust addr and length so we get all cache lines even for
* small ranges spanning two cache lines.
*/
len += addr & CVMX_CACHE_LINE_MASK;
addr &= ~CVMX_CACHE_LINE_MASK;
ptr = (volatile char *)cvmx_phys_to_ptr(addr);
ptr = cvmx_phys_to_ptr(addr);
/*
* Invalidate L1 cache to make sure all loads result in data
* being in L2.
*/
CVMX_DCACHE_INVALIDATE;
while (len > 0) {
dummy += *ptr;
ACCESS_ONCE(*ptr);
len -= CVMX_CACHE_LINE_SIZE;
ptr += CVMX_CACHE_LINE_SIZE;
}

2
arch/mips/include/asm/dsp.h
View File

@ -16,7 +16,7 @@
#include <asm/mipsregs.h>
#define DSP_DEFAULT 0x00000000
#define DSP_MASK 0x3ff
#define DSP_MASK 0x3f
#define __enable_dsp_hazard() \
do { \

1
arch/mips/include/asm/inst.h
View File

@ -353,6 +353,7 @@ union mips_instruction {
struct u_format u_format;
struct c_format c_format;
struct r_format r_format;
struct p_format p_format;
struct f_format f_format;
struct ma_format ma_format;
struct b_format b_format;

2
arch/mips/include/asm/mach-pnx833x/war.h
View File

@ -21,4 +21,4 @@
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */
#endif /* __ASM_MIPS_MACH_PNX833X_WAR_H */

1
arch/mips/include/asm/pgtable-64.h
View File

@ -230,6 +230,7 @@ static inline void pud_clear(pud_t *pudp)
#else
#define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT))
#define pfn_pte(pfn, prot) __pte(((pfn) << _PFN_SHIFT) | pgprot_val(prot))
#define pfn_pmd(pfn, prot) __pmd(((pfn) << _PFN_SHIFT) | pgprot_val(prot))
#endif
#define __pgd_offset(address) pgd_index(address)

1
arch/mips/include/uapi/asm/Kbuild
View File

@ -3,6 +3,7 @@ include include/uapi/asm-generic/Kbuild.asm
header-y += auxvec.h
header-y += bitsperlong.h
header-y += break.h
header-y += byteorder.h
header-y += cachectl.h
header-y += errno.h

0
arch/mips/include/asm/break.h → arch/mips/include/uapi/asm/break.h
View File

36
arch/mips/kernel/ftrace.c
View File

@ -25,6 +25,12 @@
#define MCOUNT_OFFSET_INSNS 4
#endif
/* Arch override because MIPS doesn't need to run this from stop_machine() */
void arch_ftrace_update_code(int command)
{
ftrace_modify_all_code(command);
}
/*
* Check if the address is in kernel space
*
@ -89,6 +95,24 @@ static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
return 0;
}
#ifndef CONFIG_64BIT
static int ftrace_modify_code_2(unsigned long ip, unsigned int new_code1,
unsigned int new_code2)
{
int faulted;
safe_store_code(new_code1, ip, faulted);
if (unlikely(faulted))
return -EFAULT;
ip += 4;
safe_store_code(new_code2, ip, faulted);
if (unlikely(faulted))
return -EFAULT;
flush_icache_range(ip, ip + 8); /* original ip + 12 */
return 0;
}
#endif
/*
* The details about the calling site of mcount on MIPS
*
@ -131,8 +155,18 @@ int ftrace_make_nop(struct module *mod,
* needed.
*/
new = in_kernel_space(ip) ? INSN_NOP : INSN_B_1F;
#ifdef CONFIG_64BIT
return ftrace_modify_code(ip, new);
#else
/*
* On 32 bit MIPS platforms, gcc adds a stack adjust
* instruction in the delay slot after the branch to
* mcount and expects mcount to restore the sp on return.
* This is based on a legacy API and does nothing but
* waste instructions so it's being removed at runtime.
*/
return ftrace_modify_code_2(ip, new, INSN_NOP);
#endif
}
int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)

7
arch/mips/kernel/mcount.S
View File

@ -46,9 +46,8 @@
PTR_L a5, PT_R9(sp)
PTR_L a6, PT_R10(sp)
PTR_L a7, PT_R11(sp)
PTR_ADDIU sp, PT_SIZE
#else
PTR_ADDIU sp, (PT_SIZE + 8)
PTR_ADDIU sp, PT_SIZE
#endif
.endm
@ -69,7 +68,9 @@ NESTED(ftrace_caller, PT_SIZE, ra)
.globl _mcount
_mcount:
b ftrace_stub
nop
addiu sp,sp,8
/* When tracing is activated, it calls ftrace_caller+8 (aka here) */
lw t1, function_trace_stop
bnez t1, ftrace_stub
nop

2
arch/mips/kernel/vpe.c
View File

@ -705,7 +705,7 @@ static int vpe_run(struct vpe * v)
printk(KERN_WARNING
"VPE loader: TC %d is already in use.\n",
t->index);
v->tc->index);
return -ENOEXEC;
}
} else {

2
arch/mips/lantiq/irq.c
View File

@ -408,7 +408,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
#endif
/* tell oprofile which irq to use */
cp0_perfcount_irq = LTQ_PERF_IRQ;
cp0_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);
/*
* if the timer irq is not one of the mips irqs we need to

2
arch/mips/lib/delay.c
View File

@ -21,7 +21,7 @@ void __delay(unsigned long loops)
" .set noreorder \n"
" .align 3 \n"
"1: bnez %0, 1b \n"
#if __SIZEOF_LONG__ == 4
#if BITS_PER_LONG == 32
" subu %0, 1 \n"
#else
" dsubu %0, 1 \n"

6
arch/mips/mm/ioremap.c
View File

@ -190,9 +190,3 @@ void __iounmap(const volatile void __iomem *addr)
EXPORT_SYMBOL(__ioremap);
EXPORT_SYMBOL(__iounmap);
int __virt_addr_valid(const volatile void *kaddr)
{
return pfn_valid(PFN_DOWN(virt_to_phys(kaddr)));
}
EXPORT_SYMBOL_GPL(__virt_addr_valid);

6
arch/mips/mm/mmap.c
View File

@ -192,3 +192,9 @@ unsigned long arch_randomize_brk(struct mm_struct *mm)
return ret;
}
int __virt_addr_valid(const volatile void *kaddr)
{
return pfn_valid(PFN_DOWN(virt_to_phys(kaddr)));
}
EXPORT_SYMBOL_GPL(__virt_addr_valid);

5
arch/mips/netlogic/xlr/setup.c
View File

@ -193,8 +193,11 @@ static void nlm_init_node(void)
void __init prom_init(void)
{
int i, *argv, *envp; /* passed as 32 bit ptrs */
int *argv, *envp; /* passed as 32 bit ptrs */
struct psb_info *prom_infop;
#ifdef CONFIG_SMP
int i;
#endif
/* truncate to 32 bit and sign extend all args */
argv = (int *)(long)(int)fw_arg1;

2
arch/mips/pci/pci-ar71xx.c
View File

@ -24,7 +24,7 @@
#include <asm/mach-ath79/pci.h>
#define AR71XX_PCI_MEM_BASE 0x10000000
#define AR71XX_PCI_MEM_SIZE 0x08000000
#define AR71XX_PCI_MEM_SIZE 0x07000000
#define AR71XX_PCI_WIN0_OFFS 0x10000000
#define AR71XX_PCI_WIN1_OFFS 0x11000000

2
arch/mips/pci/pci-ar724x.c
View File

@ -21,7 +21,7 @@
#define AR724X_PCI_CTRL_SIZE 0x100
#define AR724X_PCI_MEM_BASE 0x10000000
#define AR724X_PCI_MEM_SIZE 0x08000000
#define AR724X_PCI_MEM_SIZE 0x04000000
#define AR724X_PCI_REG_RESET 0x18
#define AR724X_PCI_REG_INT_STATUS 0x4c

16
arch/parisc/kernel/entry.S
View File

@ -1865,7 +1865,7 @@ syscall_restore:
/* Are we being ptraced? */
ldw TASK_FLAGS(%r1),%r19
ldi (_TIF_SINGLESTEP|_TIF_BLOCKSTEP),%r2
ldi _TIF_SYSCALL_TRACE_MASK,%r2
and,COND(=) %r19,%r2,%r0
b,n syscall_restore_rfi
@ -1978,15 +1978,23 @@ syscall_restore_rfi:
/* sr2 should be set to zero for userspace syscalls */
STREG %r0,TASK_PT_SR2(%r1)
pt_regs_ok:
LDREG TASK_PT_GR31(%r1),%r2
depi 3,31,2,%r2 /* ensure return to user mode. */
STREG %r2,TASK_PT_IAOQ0(%r1)
ldo 4(%r2),%r2
STREG %r2,TASK_PT_IAOQ1(%r1)
copy %r25,%r16
b intr_restore
nop
copy %r25,%r16
pt_regs_ok:
LDREG TASK_PT_IAOQ0(%r1),%r2
depi 3,31,2,%r2 /* ensure return to user mode. */
STREG %r2,TASK_PT_IAOQ0(%r1)
LDREG TASK_PT_IAOQ1(%r1),%r2
depi 3,31,2,%r2
STREG %r2,TASK_PT_IAOQ1(%r1)
b intr_restore
copy %r25,%r16
.import schedule,code
syscall_do_resched:

6
arch/parisc/kernel/irq.c
View File

@ -410,11 +410,13 @@ void __init init_IRQ(void)
{
local_irq_disable(); /* PARANOID - should already be disabled */
mtctl(~0UL, 23); /* EIRR : clear all pending external intr */
claim_cpu_irqs();
#ifdef CONFIG_SMP
if (!cpu_eiem)
if (!cpu_eiem) {
claim_cpu_irqs();
cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ);
}
#else
claim_cpu_irqs();
cpu_eiem = EIEM_MASK(TIMER_IRQ);
#endif
set_eiem(cpu_eiem); /* EIEM : enable all external intr */

2
arch/parisc/kernel/ptrace.c
View File

@ -26,7 +26,7 @@
#include <asm/asm-offsets.h>
/* PSW bits we allow the debugger to modify */
#define USER_PSW_BITS (PSW_N | PSW_V | PSW_CB)
#define USER_PSW_BITS (PSW_N | PSW_B | PSW_V | PSW_CB)
/*
* Called by kernel/ptrace.c when detaching..

4
arch/parisc/kernel/signal.c
View File

@ -190,8 +190,10 @@ get_sigframe(struct k_sigaction *ka, unsigned long sp, size_t frame_size)
DBG(1,"get_sigframe: ka = %#lx, sp = %#lx, frame_size = %#lx\n",
(unsigned long)ka, sp, frame_size);
/* Align alternate stack and reserve 64 bytes for the signal
handler's frame marker. */
if ((ka->sa.sa_flags & SA_ONSTACK) != 0 && ! sas_ss_flags(sp))
sp = current->sas_ss_sp; /* Stacks grow up! */
sp = (current->sas_ss_sp + 0x7f) & ~0x3f; /* Stacks grow up! */
DBG(1,"get_sigframe: Returning sp = %#lx\n", (unsigned long)sp);
return (void __user *) sp; /* Stacks grow up. Fun. */

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