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Merge branch 'remotes/lorenzo/pci/cadence'
- Fix Cadence PHY handling during probe (Alan Douglas) - Signal Cadence Endpoint interrupts via AXI region 0 instead of last region (Alan Douglas) - Write Cadence Endpoint MSI interrupts with 32 bits of data (Alan Douglas) * remotes/lorenzo/pci/cadence: PCI: cadence: Write MSI data with 32bits PCI: cadence: Use AXI region 0 to signal interrupts from EP PCI: cadence: Correct probe behaviour when failing to get PHY
This commit is contained in:
commit
61ce580957
@ -258,7 +258,6 @@ static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn,
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u8 intx, bool is_asserted)
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u8 intx, bool is_asserted)
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{
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{
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struct cdns_pcie *pcie = &ep->pcie;
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struct cdns_pcie *pcie = &ep->pcie;
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u32 r = ep->max_regions - 1;
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u32 offset;
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u32 offset;
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u16 status;
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u16 status;
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u8 msg_code;
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u8 msg_code;
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@ -268,8 +267,8 @@ static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn,
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/* Set the outbound region if needed. */
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/* Set the outbound region if needed. */
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if (unlikely(ep->irq_pci_addr != CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY ||
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if (unlikely(ep->irq_pci_addr != CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY ||
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ep->irq_pci_fn != fn)) {
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ep->irq_pci_fn != fn)) {
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/* Last region was reserved for IRQ writes. */
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/* First region was reserved for IRQ writes. */
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cdns_pcie_set_outbound_region_for_normal_msg(pcie, fn, r,
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cdns_pcie_set_outbound_region_for_normal_msg(pcie, fn, 0,
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ep->irq_phys_addr);
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ep->irq_phys_addr);
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ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY;
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ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY;
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ep->irq_pci_fn = fn;
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ep->irq_pci_fn = fn;
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@ -347,8 +346,8 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
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/* Set the outbound region if needed. */
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/* Set the outbound region if needed. */
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if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) ||
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if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) ||
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ep->irq_pci_fn != fn)) {
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ep->irq_pci_fn != fn)) {
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/* Last region was reserved for IRQ writes. */
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/* First region was reserved for IRQ writes. */
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cdns_pcie_set_outbound_region(pcie, fn, ep->max_regions - 1,
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cdns_pcie_set_outbound_region(pcie, fn, 0,
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false,
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false,
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ep->irq_phys_addr,
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ep->irq_phys_addr,
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pci_addr & ~pci_addr_mask,
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pci_addr & ~pci_addr_mask,
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@ -356,7 +355,7 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
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ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
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ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
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ep->irq_pci_fn = fn;
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ep->irq_pci_fn = fn;
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}
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}
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writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
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writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
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return 0;
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return 0;
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}
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}
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@ -517,6 +516,8 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
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goto free_epc_mem;
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goto free_epc_mem;
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}
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}
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ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE;
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ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE;
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/* Reserve region 0 for IRQs */
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set_bit(0, &ep->ob_region_map);
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return 0;
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return 0;
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@ -190,14 +190,16 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
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for (i = 0; i < phy_count; i++) {
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for (i = 0; i < phy_count; i++) {
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of_property_read_string_index(np, "phy-names", i, &name);
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of_property_read_string_index(np, "phy-names", i, &name);
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phy[i] = devm_phy_optional_get(dev, name);
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phy[i] = devm_phy_get(dev, name);
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if (IS_ERR(phy))
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if (IS_ERR(phy[i])) {
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return PTR_ERR(phy);
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ret = PTR_ERR(phy[i]);
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goto err_phy;
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}
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link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
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link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
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if (!link[i]) {
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if (!link[i]) {
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devm_phy_put(dev, phy[i]);
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ret = -EINVAL;
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ret = -EINVAL;
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goto err_link;
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goto err_phy;
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}
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}
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}
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}
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@ -207,13 +209,15 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
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ret = cdns_pcie_enable_phy(pcie);
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ret = cdns_pcie_enable_phy(pcie);
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if (ret)
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if (ret)
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goto err_link;
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goto err_phy;
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return 0;
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return 0;
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err_link:
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err_phy:
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while (--i >= 0)
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while (--i >= 0) {
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device_link_del(link[i]);
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device_link_del(link[i]);
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devm_phy_put(dev, phy[i]);
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}
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return ret;
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return ret;
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}
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}
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