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Merge branch 'mv88e6xxx-dsa-bindings'
Linus Walleij says: ==================== Create a binding for the Marvell MV88E6xxx DSA switches The Marvell switches are lacking DT bindings. I need proper schema checking to add LED support to the Marvell switch. Just how it is, it can't go on like this. Some Device Tree fixes are included in the series, these remove the major and most annoying warnings fallout noise: some warnings remain, and these are of more serious nature, such as missing phy-mode. They can be applied individually, or to the networking tree with the rest of the patches. Thanks to Andrew Lunn, Vladimir Oltean and Russell King for excellent review and feedback! --- Changes in v7: - Fix the elaborate spacing to satisfy yamllint in the ports/ethernet-ports requirement. - Link to v6: https://lore.kernel.org/r/20231024-marvell-88e6152-wan-led-v6-0-993ab0949344@linaro.org Changes in v6: - Fix ports/ethernet-ports requirement with proper indenting (hopefully). - Link to v5: https://lore.kernel.org/r/20231023-marvell-88e6152-wan-led-v5-0-0e82952015a7@linaro.org Changes in v5: - Consistently rename switch@n to ethernet-switch@n in all cleanup patches - Consistently rename ports to ethernet-ports in all cleanup patches - Consistently rename all port@n to ethernet-port@n in all cleanup patches - Consistently rename all phy@n to ethernet-phy@n in all cleanup patches - Restore the nodename on the Turris MOX which has a U-Boot binary using the nodename as ABI, put in a blurb warning about this so no-one else tries to change it in the future. - Drop dsa.yaml direct references where we reference dsa.yaml#/$defs/ethernet-ports - Replace the conjured MV88E6xxx example by a better one based on imx6qdl plus strictly named nodes and added reset-gpios for a more complete example, and another example using the interrupt controller based on armada-381-netgear-gs110emx.dts - Bump lineage to 2008 as Vladimir says the code was developed starting 2008. - Link to v4: https://lore.kernel.org/r/20231018-marvell-88e6152-wan-led-v4-0-3ee0c67383be@linaro.org Changes in v4: - Rebase the series on top of Rob's series "dt-bindings: net: Child node schema cleanups" (or the hex numbered ports will not work) - Fix up a whitespacing error corrupting v3... - Add a new patch making the generic DSA binding require ports or ethernet-ports in the switch node. - Drop any corrections of port@a in the patches. - Drop oneOf in the compatible enum for mv88e6xxx - Use ethernet-switch, ethernet-ports and ethernet-phy in the examples - Transclude the dsa.yaml#/$defs/ethernet-ports define for ports - Move the DTS and binding fixes first, before the actual bindings, so they apply without (too many) warnings as fallout. - Drop stray colon in text. - Drop example port in the mveusb binding. - Link to v3: https://lore.kernel.org/r/20231016-marvell-88e6152-wan-led-v3-0-38cd449dfb15@linaro.org Changes in v3: - Fix up a related mvusb example in a different binding that the scripts were complaining about. - Fix up the wording on internal vs external MDIO buses in the mv88e6xxx binding document. - Remove pointless label and put the right rev-mii into the MV88E6060 schema. - Link to v2: https://lore.kernel.org/r/20231014-marvell-88e6152-wan-led-v2-0-7fca08b68849@linaro.org Changes in v2: - Break out a separate Marvell MV88E6060 binding file. I stand corrected. - Drop the idea to rely on nodename mdio-external for the external MDIO bus, keep the compatible, drop patch for the driver. - Fix more Marvell DT mistakes. - Fix NXP DT mistakes in a separate patch. - Fix Marvell ARM64 mistakes in a separate patch. - Link to v1: https://lore.kernel.org/r/20231013-marvell-88e6152-wan-led-v1-0-0712ba99857c@linaro.org ==================== Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
61450abfc9
@ -46,4 +46,10 @@ $defs:
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||||
$ref: dsa-port.yaml#
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unevaluatedProperties: false
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oneOf:
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- required:
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- ports
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- required:
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- ethernet-ports
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...
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@ -0,0 +1,88 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/dsa/marvell,mv88e6060.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell MV88E6060 DSA switch
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maintainers:
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- Andrew Lunn <andrew@lunn.ch>
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description:
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The Marvell MV88E6060 switch has been produced and sold by Marvell
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since at least 2008. The switch has one pin ADDR4 that controls the
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MDIO address of the switch to be 0x10 or 0x00, and on the MDIO bus
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connected to the switch, the PHYs inside the switch appear as
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independent devices on address 0x00-0x04 or 0x10-0x14, so in difference
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from many other DSA switches this switch does not have an internal
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MDIO bus for the PHY devices.
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properties:
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compatible:
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const: marvell,mv88e6060
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description:
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The MV88E6060 is the oldest Marvell DSA switch product, and
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as such a bit limited in features compared to later hardware.
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reg:
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maxItems: 1
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reset-gpios:
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description:
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GPIO to be used to reset the whole device
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maxItems: 1
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allOf:
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- $ref: dsa.yaml#/$defs/ethernet-ports
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-switch@16 {
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compatible = "marvell,mv88e6060";
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reg = <16>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-port@0 {
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reg = <0>;
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label = "lan1";
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};
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ethernet-port@1 {
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reg = <1>;
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label = "lan2";
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};
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ethernet-port@2 {
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reg = <2>;
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label = "lan3";
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};
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ethernet-port@3 {
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reg = <3>;
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label = "lan4";
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};
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ethernet-port@5 {
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reg = <5>;
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phy-mode = "rev-mii";
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ethernet = <ðc>;
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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};
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};
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};
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};
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330
Documentation/devicetree/bindings/net/dsa/marvell,mv88e6xxx.yaml
Normal file
330
Documentation/devicetree/bindings/net/dsa/marvell,mv88e6xxx.yaml
Normal file
@ -0,0 +1,330 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/dsa/marvell,mv88e6xxx.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell MV88E6xxx DSA switch family
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maintainers:
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- Andrew Lunn <andrew@lunn.ch>
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description:
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The Marvell MV88E6xxx switch series has been produced and sold
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by Marvell since at least 2008. The switch has a few compatibles which
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just indicate the base address of the switch, then operating systems
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can investigate switch ID registers to find out which actual version
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of the switch it is dealing with.
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properties:
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compatible:
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enum:
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- marvell,mv88e6085
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- marvell,mv88e6190
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- marvell,mv88e6250
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description: |
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marvell,mv88e6085: This switch uses base address 0x10.
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This switch and its siblings will be autodetected from
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ID registers found in the switch, so only "marvell,mv88e6085" should be
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specified. This includes the following list of MV88Exxxx switches:
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6085, 6095, 6097, 6123, 6131, 6141, 6161, 6165, 6171, 6172, 6175, 6176,
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6185, 6240, 6320, 6321, 6341, 6350, 6351, 6352
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marvell,mv88e6190: This switch uses base address 0x00.
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This switch and its siblings will be autodetected from
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ID registers found in the switch, so only "marvell,mv88e6190" should be
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specified. This includes the following list of MV88Exxxx switches:
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6190, 6190X, 6191, 6290, 6361, 6390, 6390X
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marvell,mv88e6250: This switch uses base address 0x08 or 0x18.
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This switch and its siblings will be autodetected from
|
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ID registers found in the switch, so only "marvell,mv88e6250" should be
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||||
specified. This includes the following list of MV88Exxxx switches:
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6220, 6250
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reg:
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maxItems: 1
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eeprom-length:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Set to the length of an EEPROM connected to the switch. Must be
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set if the switch can not detect the presence and/or size of a connected
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EEPROM, otherwise optional.
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reset-gpios:
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description:
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GPIO to be used to reset the whole device
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maxItems: 1
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interrupts:
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description: The switch provides an external interrupt line, but it is
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not always used by target systems.
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maxItems: 1
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interrupt-controller:
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description: The switch has an internal interrupt controller used by
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the different sub-blocks.
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'#interrupt-cells':
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description: The internal interrupt controller only supports triggering
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on active high level interrupts so the second cell must alway be set to
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IRQ_TYPE_LEVEL_HIGH.
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const: 2
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mdio:
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$ref: /schemas/net/mdio.yaml#
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unevaluatedProperties: false
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description: Marvell MV88E6xxx switches have an varying combination of
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internal and external MDIO buses, in some cases a combined bus that
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can be used both internally and externally. This node is for the
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primary bus, used internally and sometimes also externally.
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mdio-external:
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$ref: /schemas/net/mdio.yaml#
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unevaluatedProperties: false
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description: Marvell MV88E6xxx switches that have a separate external
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MDIO bus use this port to access external components on the MDIO bus.
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properties:
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compatible:
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const: marvell,mv88e6xxx-mdio-external
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required:
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- compatible
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allOf:
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- $ref: dsa.yaml#/$defs/ethernet-ports
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required:
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||||
- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-switch@0 {
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compatible = "marvell,mv88e6085";
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reg = <0>;
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reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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sw_phy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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sw_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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sw_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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sw_phy3: ethernet-phy@3 {
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reg = <0x3>;
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};
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};
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-port@0 {
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reg = <0>;
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label = "lan4";
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phy-handle = <&sw_phy0>;
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phy-mode = "internal";
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};
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ethernet-port@1 {
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reg = <1>;
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label = "lan3";
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phy-handle = <&sw_phy1>;
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phy-mode = "internal";
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};
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ethernet-port@2 {
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reg = <2>;
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label = "lan2";
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phy-handle = <&sw_phy2>;
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phy-mode = "internal";
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};
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ethernet-port@3 {
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reg = <3>;
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label = "lan1";
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phy-handle = <&sw_phy3>;
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phy-mode = "internal";
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};
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ethernet-port@5 {
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reg = <5>;
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ethernet = <&fec>;
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phy-mode = "rgmii-id";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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||||
};
|
||||
};
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||||
};
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||||
};
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-switch@0 {
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compatible = "marvell,mv88e6190";
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupt-parent = <&gpio1>;
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interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-0 = <&switch_interrupt_pins>;
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pinctrl-names = "default";
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reg = <0>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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|
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switch0phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
|
||||
|
||||
switch0phy2: ethernet-phy@2 {
|
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reg = <0x2>;
|
||||
};
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||||
|
||||
switch0phy3: ethernet-phy@3 {
|
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reg = <0x3>;
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||||
};
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|
||||
switch0phy4: ethernet-phy@4 {
|
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reg = <0x4>;
|
||||
};
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||||
|
||||
switch0phy5: ethernet-phy@5 {
|
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reg = <0x5>;
|
||||
};
|
||||
|
||||
switch0phy6: ethernet-phy@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
switch0phy7: ethernet-phy@7 {
|
||||
reg = <0x7>;
|
||||
};
|
||||
|
||||
switch0phy8: ethernet-phy@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio-external {
|
||||
compatible = "marvell,mv88e6xxx-mdio-external";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy1: ethernet-phy@b {
|
||||
reg = <0xb>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
};
|
||||
|
||||
phy2: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
};
|
||||
};
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethernet-port@0 {
|
||||
ethernet = <ð0>;
|
||||
phy-mode = "rgmii";
|
||||
reg = <0>;
|
||||
|
||||
fixed-link {
|
||||
full-duplex;
|
||||
pause;
|
||||
speed = <1000>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet-port@1 {
|
||||
label = "lan1";
|
||||
phy-handle = <&switch0phy1>;
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
ethernet-port@2 {
|
||||
label = "lan2";
|
||||
phy-handle = <&switch0phy2>;
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
ethernet-port@3 {
|
||||
label = "lan3";
|
||||
phy-handle = <&switch0phy3>;
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
ethernet-port@4 {
|
||||
label = "lan4";
|
||||
phy-handle = <&switch0phy4>;
|
||||
reg = <4>;
|
||||
};
|
||||
|
||||
ethernet-port@5 {
|
||||
label = "lan5";
|
||||
phy-handle = <&switch0phy5>;
|
||||
reg = <5>;
|
||||
};
|
||||
|
||||
ethernet-port@6 {
|
||||
label = "lan6";
|
||||
phy-handle = <&switch0phy6>;
|
||||
reg = <6>;
|
||||
};
|
||||
|
||||
ethernet-port@7 {
|
||||
label = "lan7";
|
||||
phy-handle = <&switch0phy7>;
|
||||
reg = <7>;
|
||||
};
|
||||
|
||||
ethernet-port@8 {
|
||||
label = "lan8";
|
||||
phy-handle = <&switch0phy8>;
|
||||
reg = <8>;
|
||||
};
|
||||
|
||||
ethernet-port@9 {
|
||||
/* 88X3310P external phy */
|
||||
label = "lan9";
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "xaui";
|
||||
reg = <9>;
|
||||
};
|
||||
|
||||
ethernet-port@a {
|
||||
/* 88X3310P external phy */
|
||||
label = "lan10";
|
||||
phy-handle = <&phy2>;
|
||||
phy-mode = "xaui";
|
||||
reg = <0xa>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1,109 +0,0 @@
|
||||
Marvell DSA Switch Device Tree Bindings
|
||||
---------------------------------------
|
||||
|
||||
WARNING: This binding is currently unstable. Do not program it into a
|
||||
FLASH never to be changed again. Once this binding is stable, this
|
||||
warning will be removed.
|
||||
|
||||
If you need a stable binding, use the old dsa.txt binding.
|
||||
|
||||
Marvell Switches are MDIO devices. The following properties should be
|
||||
placed as a child node of an mdio device.
|
||||
|
||||
The properties described here are those specific to Marvell devices.
|
||||
Additional required and optional properties can be found in dsa.txt.
|
||||
|
||||
The compatibility string is used only to find an identification register,
|
||||
which is at a different MDIO base address in different switch families.
|
||||
- "marvell,mv88e6085" : Switch has base address 0x10. Use with models:
|
||||
6085, 6095, 6097, 6123, 6131, 6141, 6161, 6165,
|
||||
6171, 6172, 6175, 6176, 6185, 6240, 6320, 6321,
|
||||
6341, 6350, 6351, 6352
|
||||
- "marvell,mv88e6190" : Switch has base address 0x00. Use with models:
|
||||
6190, 6190X, 6191, 6290, 6361, 6390, 6390X
|
||||
- "marvell,mv88e6250" : Switch has base address 0x08 or 0x18. Use with model:
|
||||
6220, 6250
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be one of "marvell,mv88e6085",
|
||||
"marvell,mv88e6190" or "marvell,mv88e6250" as
|
||||
indicated above
|
||||
- reg : Address on the MII bus for the switch.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- reset-gpios : Should be a gpio specifier for a reset line
|
||||
- interrupts : Interrupt from the switch
|
||||
- interrupt-controller : Indicates the switch is itself an interrupt
|
||||
controller. This is used for the PHY interrupts.
|
||||
#interrupt-cells = <2> : Controller uses two cells, number and flag
|
||||
- eeprom-length : Set to the length of an EEPROM connected to the
|
||||
switch. Must be set if the switch can not detect
|
||||
the presence and/or size of a connected EEPROM,
|
||||
otherwise optional.
|
||||
- mdio : Container of PHY and devices on the switches MDIO
|
||||
bus.
|
||||
- mdio? : Container of PHYs and devices on the external MDIO
|
||||
bus. The node must contains a compatible string of
|
||||
"marvell,mv88e6xxx-mdio-external"
|
||||
|
||||
Example:
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
switch0: switch@0 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
reg = <0>;
|
||||
reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
switch1phy0: switch1phy0@0 {
|
||||
reg = <0>;
|
||||
interrupt-parent = <&switch0>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
switch0: switch@0 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
reg = <0>;
|
||||
reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
switch1phy0: switch1phy0@0 {
|
||||
reg = <0>;
|
||||
interrupt-parent = <&switch0>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio1 {
|
||||
compatible = "marvell,mv88e6xxx-mdio-external";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
switch1phy9: switch1phy0@9 {
|
||||
reg = <9>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -50,11 +50,14 @@ examples:
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch@0 {
|
||||
ethernet-switch@0 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
reg = <0x0>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Port definitions */
|
||||
};
|
||||
|
||||
|
||||
@ -12626,7 +12626,8 @@ MARVELL 88E6XXX ETHERNET SWITCH FABRIC DRIVER
|
||||
M: Andrew Lunn <andrew@lunn.ch>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/net/dsa/marvell.txt
|
||||
F: Documentation/devicetree/bindings/net/dsa/marvell,mv88e6060.yaml
|
||||
F: Documentation/devicetree/bindings/net/dsa/marvell,mv88e6xxx.yaml
|
||||
F: Documentation/networking/devlink/mv88e6xxx.rst
|
||||
F: drivers/net/dsa/mv88e6xxx/
|
||||
F: include/linux/dsa/mv88e6xxx.h
|
||||
|
||||
@ -149,39 +149,37 @@
|
||||
};
|
||||
};
|
||||
|
||||
switch: switch@10 {
|
||||
switch: ethernet-switch@10 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x10>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
ethernet-port@0 {
|
||||
reg = <0>;
|
||||
label = "lan0";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
ethernet = <ð1>;
|
||||
phy-mode = "rgmii-id";
|
||||
@ -196,25 +194,25 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switchphy0: switchphy@0 {
|
||||
switchphy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
interrupt-parent = <&switch>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
switchphy1: switchphy@1 {
|
||||
switchphy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&switch>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
switchphy2: switchphy@2 {
|
||||
switchphy2: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
interrupt-parent = <&switch>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
switchphy3: switchphy@3 {
|
||||
switchphy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
interrupt-parent = <&switch>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
@ -77,51 +77,49 @@
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
status = "okay";
|
||||
|
||||
switch@0 {
|
||||
ethernet-switch@0 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
#address-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-0 = <&switch_interrupt_pins>;
|
||||
pinctrl-names = "default";
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0phy1: switch0phy1@1 {
|
||||
switch0phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
switch0phy2: switch0phy2@2 {
|
||||
switch0phy2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
switch0phy3: switch0phy3@3 {
|
||||
switch0phy3: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
switch0phy4: switch0phy4@4 {
|
||||
switch0phy4: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
switch0phy5: switch0phy5@5 {
|
||||
switch0phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
switch0phy6: switch0phy6@6 {
|
||||
switch0phy6: ethernet-phy@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
switch0phy7: switch0phy7@7 {
|
||||
switch0phy7: ethernet-phy@7 {
|
||||
reg = <0x7>;
|
||||
};
|
||||
|
||||
switch0phy8: switch0phy8@8 {
|
||||
switch0phy8: ethernet-phy@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
};
|
||||
@ -142,11 +140,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
ethernet-port@0 {
|
||||
ethernet = <ð0>;
|
||||
phy-mode = "rgmii";
|
||||
reg = <0>;
|
||||
@ -158,55 +156,55 @@
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
label = "lan1";
|
||||
phy-handle = <&switch0phy1>;
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
label = "lan2";
|
||||
phy-handle = <&switch0phy2>;
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
label = "lan3";
|
||||
phy-handle = <&switch0phy3>;
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
label = "lan4";
|
||||
phy-handle = <&switch0phy4>;
|
||||
reg = <4>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
label = "lan5";
|
||||
phy-handle = <&switch0phy5>;
|
||||
reg = <5>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
ethernet-port@6 {
|
||||
label = "lan6";
|
||||
phy-handle = <&switch0phy6>;
|
||||
reg = <6>;
|
||||
};
|
||||
|
||||
port@7 {
|
||||
ethernet-port@7 {
|
||||
label = "lan7";
|
||||
phy-handle = <&switch0phy7>;
|
||||
reg = <7>;
|
||||
};
|
||||
|
||||
port@8 {
|
||||
ethernet-port@8 {
|
||||
label = "lan8";
|
||||
phy-handle = <&switch0phy8>;
|
||||
reg = <8>;
|
||||
};
|
||||
|
||||
port@9 {
|
||||
ethernet-port@9 {
|
||||
/* 88X3310P external phy */
|
||||
label = "lan9";
|
||||
phy-handle = <&phy1>;
|
||||
@ -214,7 +212,7 @@
|
||||
reg = <9>;
|
||||
};
|
||||
|
||||
port@a {
|
||||
ethernet-port@a {
|
||||
/* 88X3310P external phy */
|
||||
label = "lan10";
|
||||
phy-handle = <&phy2>;
|
||||
|
||||
@ -7,66 +7,66 @@
|
||||
};
|
||||
|
||||
&mdio {
|
||||
switch0: switch0@4 {
|
||||
switch0: ethernet-switch@4 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
reg = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cf_gtr_switch_reset_pins>;
|
||||
reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "lan8";
|
||||
phy-handle = <&switch0phy0>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "lan7";
|
||||
phy-handle = <&switch0phy1>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "lan6";
|
||||
phy-handle = <&switch0phy2>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "lan5";
|
||||
phy-handle = <&switch0phy3>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
label = "lan4";
|
||||
phy-handle = <&switch0phy4>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
ethernet-port@6 {
|
||||
reg = <6>;
|
||||
label = "lan3";
|
||||
phy-handle = <&switch0phy5>;
|
||||
};
|
||||
|
||||
port@7 {
|
||||
ethernet-port@7 {
|
||||
reg = <7>;
|
||||
label = "lan2";
|
||||
phy-handle = <&switch0phy6>;
|
||||
};
|
||||
|
||||
port@8 {
|
||||
ethernet-port@8 {
|
||||
reg = <8>;
|
||||
label = "lan1";
|
||||
phy-handle = <&switch0phy7>;
|
||||
};
|
||||
|
||||
port@10 {
|
||||
ethernet-port@10 {
|
||||
reg = <10>;
|
||||
phy-mode = "2500base-x";
|
||||
|
||||
@ -83,35 +83,35 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0phy0: switch0phy0@1 {
|
||||
switch0phy0: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
switch0phy1: switch0phy1@2 {
|
||||
switch0phy1: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
switch0phy2: switch0phy2@3 {
|
||||
switch0phy2: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
switch0phy3: switch0phy3@4 {
|
||||
switch0phy3: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
switch0phy4: switch0phy4@5 {
|
||||
switch0phy4: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
switch0phy5: switch0phy5@6 {
|
||||
switch0phy5: ethernet-phy@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
switch0phy6: switch0phy6@7 {
|
||||
switch0phy6: ethernet-phy@7 {
|
||||
reg = <0x7>;
|
||||
};
|
||||
|
||||
switch0phy7: switch0phy7@8 {
|
||||
switch0phy7: ethernet-phy@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -11,42 +11,42 @@
|
||||
};
|
||||
|
||||
&mdio {
|
||||
switch0: switch0@4 {
|
||||
switch0: ethernet-switch@4 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
reg = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cf_gtr_switch_reset_pins>;
|
||||
reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "lan2";
|
||||
phy-handle = <&switch0phy0>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "lan1";
|
||||
phy-handle = <&switch0phy1>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "lan4";
|
||||
phy-handle = <&switch0phy2>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "lan3";
|
||||
phy-handle = <&switch0phy3>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
phy-mode = "2500base-x";
|
||||
ethernet = <ð1>;
|
||||
@ -63,19 +63,19 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0phy0: switch0phy0@11 {
|
||||
switch0phy0: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
|
||||
switch0phy1: switch0phy1@12 {
|
||||
switch0phy1: ethernet-phy@12 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
switch0phy2: switch0phy2@13 {
|
||||
switch0phy2: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
|
||||
switch0phy3: switch0phy3@14 {
|
||||
switch0phy3: ethernet-phy@14 {
|
||||
reg = <0x14>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -158,42 +158,40 @@
|
||||
&mdio {
|
||||
status = "okay";
|
||||
|
||||
switch@0 {
|
||||
ethernet-switch@0 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
ethernet-port@0 {
|
||||
reg = <0>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "wan";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
phy-mode = "sgmii";
|
||||
ethernet = <ð2>;
|
||||
|
||||
@ -435,12 +435,10 @@
|
||||
};
|
||||
|
||||
/* Switch MV88E6176 at address 0x10 */
|
||||
switch@10 {
|
||||
ethernet-switch@10 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&swint_pins>;
|
||||
compatible = "marvell,mv88e6085";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dsa,member = <0 0>;
|
||||
reg = <0x10>;
|
||||
@ -448,36 +446,36 @@
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports@0 {
|
||||
ethernet-port@0 {
|
||||
reg = <0>;
|
||||
label = "lan0";
|
||||
};
|
||||
|
||||
ports@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
ports@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
ports@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
ports@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
ports@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
ethernet = <ð1>;
|
||||
phy-mode = "rgmii-id";
|
||||
@ -488,7 +486,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
ports@6 {
|
||||
ethernet-port@6 {
|
||||
reg = <6>;
|
||||
ethernet = <ð0>;
|
||||
phy-mode = "rgmii-id";
|
||||
|
||||
@ -92,44 +92,42 @@
|
||||
&mdio {
|
||||
status = "okay";
|
||||
|
||||
switch@4 {
|
||||
ethernet-switch@4 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
ethernet-port@0 {
|
||||
reg = <0>;
|
||||
label = "lan5";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
ethernet = <ð1>;
|
||||
phy-mode = "1000base-x";
|
||||
@ -140,7 +138,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
port@6 {
|
||||
ethernet-port@6 {
|
||||
/* 88E1512 external phy */
|
||||
reg = <6>;
|
||||
label = "lan6";
|
||||
|
||||
@ -265,42 +265,40 @@
|
||||
&mdio {
|
||||
status = "okay";
|
||||
|
||||
switch@0 {
|
||||
ethernet-switch@0 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
ethernet-port@0 {
|
||||
reg = <0>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "internet";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
phy-mode = "rgmii-id";
|
||||
ethernet = <ð0>;
|
||||
|
||||
@ -162,7 +162,7 @@
|
||||
suppress-preamble;
|
||||
status = "okay";
|
||||
|
||||
switch0: switch0@0 {
|
||||
switch0: ethernet-switch@0 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_switch>;
|
||||
@ -173,26 +173,26 @@
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
ethernet-port@0 {
|
||||
reg = <0>;
|
||||
label = "eth_cu_1000_1";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "eth_cu_1000_2";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "eth_cu_1000_3";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
label = "eth_fc_1000_1";
|
||||
phy-mode = "1000base-x";
|
||||
@ -200,7 +200,7 @@
|
||||
sfp = <&sff>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
ethernet-port@6 {
|
||||
reg = <6>;
|
||||
phy-mode = "rmii";
|
||||
ethernet = <&fec1>;
|
||||
|
||||
@ -47,17 +47,17 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0: switch0@0 {
|
||||
switch0: ethernet-switch@0 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
reg = <0>;
|
||||
dsa,member = <0 0>;
|
||||
eeprom-length = <65536>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
ethernet-port@0 {
|
||||
reg = <0>;
|
||||
phy-mode = "rmii";
|
||||
ethernet = <&fec1>;
|
||||
@ -68,37 +68,37 @@
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "aib2main_1";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "aib2main_2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "eth_cu_1000_5";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "eth_cu_1000_6";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
label = "eth_cu_1000_4";
|
||||
};
|
||||
|
||||
port@6 {
|
||||
ethernet-port@6 {
|
||||
reg = <6>;
|
||||
label = "eth_cu_1000_7";
|
||||
};
|
||||
|
||||
port@7 {
|
||||
ethernet-port@7 {
|
||||
reg = <7>;
|
||||
label = "modem_pic";
|
||||
|
||||
@ -108,7 +108,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
switch0port10: port@10 {
|
||||
switch0port10: ethernet-port@10 {
|
||||
reg = <10>;
|
||||
label = "dsa";
|
||||
phy-mode = "xgmii";
|
||||
@ -130,32 +130,32 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch1: switch1@0 {
|
||||
switch1: ethernet-switch@0 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
reg = <0>;
|
||||
dsa,member = <0 1>;
|
||||
eeprom-length = <65536>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "eth_cu_1000_3";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "eth_cu_100_2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "eth_cu_100_3";
|
||||
};
|
||||
|
||||
switch1port9: port@9 {
|
||||
switch1port9: ethernet-port@9 {
|
||||
reg = <9>;
|
||||
label = "dsa";
|
||||
phy-mode = "xgmii";
|
||||
@ -168,7 +168,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
switch1port10: port@10 {
|
||||
switch1port10: ethernet-port@10 {
|
||||
reg = <10>;
|
||||
label = "dsa";
|
||||
phy-mode = "xgmii";
|
||||
@ -188,17 +188,17 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch2: switch2@0 {
|
||||
switch2: ethernet-switch@0 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
reg = <0>;
|
||||
dsa,member = <0 2>;
|
||||
eeprom-length = <65536>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "eth_fc_1000_2";
|
||||
phy-mode = "1000base-x";
|
||||
@ -206,7 +206,7 @@
|
||||
sfp = <&sff1>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "eth_fc_1000_3";
|
||||
phy-mode = "1000base-x";
|
||||
@ -214,7 +214,7 @@
|
||||
sfp = <&sff2>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "eth_fc_1000_4";
|
||||
phy-mode = "1000base-x";
|
||||
@ -222,7 +222,7 @@
|
||||
sfp = <&sff3>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
label = "eth_fc_1000_5";
|
||||
phy-mode = "1000base-x";
|
||||
@ -230,7 +230,7 @@
|
||||
sfp = <&sff4>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
ethernet-port@6 {
|
||||
reg = <6>;
|
||||
label = "eth_fc_1000_6";
|
||||
phy-mode = "1000base-x";
|
||||
@ -238,7 +238,7 @@
|
||||
sfp = <&sff5>;
|
||||
};
|
||||
|
||||
port@7 {
|
||||
ethernet-port@7 {
|
||||
reg = <7>;
|
||||
label = "eth_fc_1000_7";
|
||||
phy-mode = "1000base-x";
|
||||
@ -246,7 +246,7 @@
|
||||
sfp = <&sff6>;
|
||||
};
|
||||
|
||||
port@9 {
|
||||
ethernet-port@9 {
|
||||
reg = <9>;
|
||||
label = "eth_fc_1000_1";
|
||||
phy-mode = "1000base-x";
|
||||
@ -254,7 +254,7 @@
|
||||
sfp = <&sff0>;
|
||||
};
|
||||
|
||||
switch2port10: port@10 {
|
||||
switch2port10: ethernet-port@10 {
|
||||
reg = <10>;
|
||||
label = "dsa";
|
||||
phy-mode = "2500base-x";
|
||||
@ -276,17 +276,17 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch3: switch3@0 {
|
||||
switch3: ethernet-switch@0 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
reg = <0>;
|
||||
dsa,member = <0 3>;
|
||||
eeprom-length = <65536>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "eth_fc_1000_8";
|
||||
phy-mode = "1000base-x";
|
||||
@ -294,7 +294,7 @@
|
||||
sfp = <&sff7>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "eth_fc_1000_9";
|
||||
phy-mode = "1000base-x";
|
||||
@ -302,7 +302,7 @@
|
||||
sfp = <&sff8>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "eth_fc_1000_10";
|
||||
phy-mode = "1000base-x";
|
||||
@ -310,7 +310,7 @@
|
||||
sfp = <&sff9>;
|
||||
};
|
||||
|
||||
switch3port9: port@9 {
|
||||
switch3port9: ethernet-port@9 {
|
||||
reg = <9>;
|
||||
label = "dsa";
|
||||
phy-mode = "2500base-x";
|
||||
@ -322,7 +322,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
switch3port10: port@10 {
|
||||
switch3port10: ethernet-port@10 {
|
||||
reg = <10>;
|
||||
label = "dsa";
|
||||
phy-mode = "xgmii";
|
||||
|
||||
@ -123,7 +123,7 @@
|
||||
suppress-preamble;
|
||||
status = "okay";
|
||||
|
||||
switch0: switch0@0 {
|
||||
switch0: ethernet-switch@0 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
pinctrl-0 = <&pinctrl_gpio_switch0>;
|
||||
pinctrl-names = "default";
|
||||
@ -134,11 +134,11 @@
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
ethernet-port@0 {
|
||||
reg = <0>;
|
||||
phy-mode = "rmii";
|
||||
ethernet = <&fec1>;
|
||||
@ -149,32 +149,32 @@
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "eth_cu_1000_1";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "eth_cu_1000_2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "eth_cu_1000_3";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "eth_cu_1000_4";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
label = "eth_cu_1000_5";
|
||||
};
|
||||
|
||||
port@6 {
|
||||
ethernet-port@6 {
|
||||
reg = <6>;
|
||||
label = "eth_cu_1000_6";
|
||||
};
|
||||
|
||||
@ -112,7 +112,7 @@
|
||||
suppress-preamble;
|
||||
status = "okay";
|
||||
|
||||
switch0: switch0@0 {
|
||||
switch0: ethernet-switch@0 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
pinctrl-0 = <&pinctrl_gpio_switch0>;
|
||||
pinctrl-names = "default";
|
||||
@ -123,11 +123,11 @@
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
ethernet-port@0 {
|
||||
reg = <0>;
|
||||
phy-mode = "rmii";
|
||||
ethernet = <&fec1>;
|
||||
@ -138,27 +138,27 @@
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "eth_cu_100_3";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
label = "eth_cu_1000_4";
|
||||
};
|
||||
|
||||
port@6 {
|
||||
ethernet-port@6 {
|
||||
reg = <6>;
|
||||
label = "eth_cu_1000_5";
|
||||
};
|
||||
|
||||
port@8 {
|
||||
ethernet-port@8 {
|
||||
reg = <8>;
|
||||
label = "eth_cu_1000_1";
|
||||
};
|
||||
|
||||
port@9 {
|
||||
ethernet-port@9 {
|
||||
reg = <9>;
|
||||
label = "eth_cu_1000_2";
|
||||
phy-handle = <&phy9>;
|
||||
@ -167,12 +167,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
mdio1 {
|
||||
mdio-external {
|
||||
compatible = "marvell,mv88e6xxx-mdio-external";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy9: phy9@0 {
|
||||
phy9: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
pinctrl-0 = <&pinctrl_gpio_phy9>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
@ -137,7 +137,7 @@
|
||||
suppress-preamble;
|
||||
status = "okay";
|
||||
|
||||
switch0: switch0@0 {
|
||||
switch0: ethernet-switch@0 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
pinctrl-0 = <&pinctrl_gpio_switch0>;
|
||||
pinctrl-names = "default";
|
||||
@ -148,11 +148,11 @@
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
ethernet-port@0 {
|
||||
reg = <0>;
|
||||
phy-mode = "rmii";
|
||||
ethernet = <&fec1>;
|
||||
@ -163,32 +163,32 @@
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "eth_cu_1000_1";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "eth_cu_1000_2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "eth_cu_1000_3";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "eth_cu_1000_4";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
label = "eth_cu_1000_5";
|
||||
};
|
||||
|
||||
port@6 {
|
||||
ethernet-port@6 {
|
||||
reg = <6>;
|
||||
label = "eth_cu_1000_6";
|
||||
};
|
||||
|
||||
@ -126,32 +126,32 @@
|
||||
|
||||
reset-gpios = <&gpiosb 23 GPIO_ACTIVE_LOW>;
|
||||
|
||||
ports {
|
||||
switch0port1: port@1 {
|
||||
ethernet-ports {
|
||||
switch0port1: ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "lan0";
|
||||
phy-handle = <&switch0phy0>;
|
||||
};
|
||||
|
||||
switch0port2: port@2 {
|
||||
switch0port2: ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "lan1";
|
||||
phy-handle = <&switch0phy1>;
|
||||
};
|
||||
|
||||
switch0port3: port@3 {
|
||||
switch0port3: ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "lan2";
|
||||
phy-handle = <&switch0phy2>;
|
||||
};
|
||||
|
||||
switch0port4: port@4 {
|
||||
switch0port4: ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "lan3";
|
||||
phy-handle = <&switch0phy3>;
|
||||
};
|
||||
|
||||
switch0port5: port@5 {
|
||||
switch0port5: ethernet-port@5 {
|
||||
reg = <5>;
|
||||
label = "wan";
|
||||
phy-handle = <&extphy>;
|
||||
@ -160,7 +160,7 @@
|
||||
};
|
||||
|
||||
mdio {
|
||||
switch0phy3: switch0phy3@14 {
|
||||
switch0phy3: ethernet-phy@14 {
|
||||
reg = <0x14>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -145,19 +145,17 @@
|
||||
};
|
||||
|
||||
&mdio {
|
||||
switch0: switch0@1 {
|
||||
switch0: ethernet-switch@1 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
dsa,member = <0 0>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0port0: port@0 {
|
||||
switch0port0: ethernet-port@0 {
|
||||
reg = <0>;
|
||||
label = "cpu";
|
||||
ethernet = <ð0>;
|
||||
@ -168,19 +166,19 @@
|
||||
};
|
||||
};
|
||||
|
||||
switch0port1: port@1 {
|
||||
switch0port1: ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "wan";
|
||||
phy-handle = <&switch0phy0>;
|
||||
};
|
||||
|
||||
switch0port2: port@2 {
|
||||
switch0port2: ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "lan0";
|
||||
phy-handle = <&switch0phy1>;
|
||||
};
|
||||
|
||||
switch0port3: port@3 {
|
||||
switch0port3: ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "lan1";
|
||||
phy-handle = <&switch0phy2>;
|
||||
@ -192,13 +190,13 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0phy0: switch0phy0@11 {
|
||||
switch0phy0: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
switch0phy1: switch0phy1@12 {
|
||||
switch0phy1: ethernet-phy@12 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
switch0phy2: switch0phy2@13 {
|
||||
switch0phy2: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -152,31 +152,29 @@
|
||||
};
|
||||
|
||||
&mdio {
|
||||
switch0: switch0@1 {
|
||||
switch0: ethernet-switch@1 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
dsa,member = <0 0>;
|
||||
|
||||
ports: ports {
|
||||
ports: ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
ethernet-port@0 {
|
||||
reg = <0>;
|
||||
label = "cpu";
|
||||
ethernet = <ð0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "wan";
|
||||
phy-handle = <&switch0phy0>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "lan0";
|
||||
phy-handle = <&switch0phy1>;
|
||||
@ -185,7 +183,7 @@
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "lan1";
|
||||
phy-handle = <&switch0phy2>;
|
||||
@ -199,13 +197,13 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0phy0: switch0phy0@11 {
|
||||
switch0phy0: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
switch0phy1: switch0phy1@12 {
|
||||
switch0phy1: ethernet-phy@12 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
switch0phy2: switch0phy2@13 {
|
||||
switch0phy2: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -304,7 +304,12 @@
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
/* switch nodes are enabled by U-Boot if modules are present */
|
||||
/*
|
||||
* NOTE: switch nodes are enabled by U-Boot if modules are present
|
||||
* DO NOT change this node name (switch0@10) even if it is not following
|
||||
* conventions! Deployed U-Boot binaries are explicitly looking for
|
||||
* this node in order to augment the device tree!
|
||||
*/
|
||||
switch0@10 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
reg = <0x10>;
|
||||
@ -317,92 +322,92 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0phy1: switch0phy1@1 {
|
||||
switch0phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
switch0phy2: switch0phy2@2 {
|
||||
switch0phy2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
switch0phy3: switch0phy3@3 {
|
||||
switch0phy3: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
switch0phy4: switch0phy4@4 {
|
||||
switch0phy4: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
switch0phy5: switch0phy5@5 {
|
||||
switch0phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
switch0phy6: switch0phy6@6 {
|
||||
switch0phy6: ethernet-phy@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
switch0phy7: switch0phy7@7 {
|
||||
switch0phy7: ethernet-phy@7 {
|
||||
reg = <0x7>;
|
||||
};
|
||||
|
||||
switch0phy8: switch0phy8@8 {
|
||||
switch0phy8: ethernet-phy@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <0x1>;
|
||||
label = "lan1";
|
||||
phy-handle = <&switch0phy1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <0x2>;
|
||||
label = "lan2";
|
||||
phy-handle = <&switch0phy2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <0x3>;
|
||||
label = "lan3";
|
||||
phy-handle = <&switch0phy3>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <0x4>;
|
||||
label = "lan4";
|
||||
phy-handle = <&switch0phy4>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <0x5>;
|
||||
label = "lan5";
|
||||
phy-handle = <&switch0phy5>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
ethernet-port@6 {
|
||||
reg = <0x6>;
|
||||
label = "lan6";
|
||||
phy-handle = <&switch0phy6>;
|
||||
};
|
||||
|
||||
port@7 {
|
||||
ethernet-port@7 {
|
||||
reg = <0x7>;
|
||||
label = "lan7";
|
||||
phy-handle = <&switch0phy7>;
|
||||
};
|
||||
|
||||
port@8 {
|
||||
ethernet-port@8 {
|
||||
reg = <0x8>;
|
||||
label = "lan8";
|
||||
phy-handle = <&switch0phy8>;
|
||||
};
|
||||
|
||||
port@9 {
|
||||
ethernet-port@9 {
|
||||
reg = <0x9>;
|
||||
label = "cpu";
|
||||
ethernet = <ð1>;
|
||||
@ -410,7 +415,7 @@
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
switch0port10: port@a {
|
||||
switch0port10: ethernet-port@a {
|
||||
reg = <0xa>;
|
||||
label = "dsa";
|
||||
phy-mode = "2500base-x";
|
||||
@ -430,7 +435,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
switch0@2 {
|
||||
ethernet-switch@2 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
reg = <0x2>;
|
||||
dsa,member = <0 0>;
|
||||
@ -442,52 +447,52 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0phy1_topaz: switch0phy1@11 {
|
||||
switch0phy1_topaz: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
|
||||
switch0phy2_topaz: switch0phy2@12 {
|
||||
switch0phy2_topaz: ethernet-phy@12 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
switch0phy3_topaz: switch0phy3@13 {
|
||||
switch0phy3_topaz: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
|
||||
switch0phy4_topaz: switch0phy4@14 {
|
||||
switch0phy4_topaz: ethernet-phy@14 {
|
||||
reg = <0x14>;
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <0x1>;
|
||||
label = "lan1";
|
||||
phy-handle = <&switch0phy1_topaz>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <0x2>;
|
||||
label = "lan2";
|
||||
phy-handle = <&switch0phy2_topaz>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <0x3>;
|
||||
label = "lan3";
|
||||
phy-handle = <&switch0phy3_topaz>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <0x4>;
|
||||
label = "lan4";
|
||||
phy-handle = <&switch0phy4_topaz>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <0x5>;
|
||||
label = "cpu";
|
||||
phy-mode = "2500base-x";
|
||||
@ -497,7 +502,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
switch1@11 {
|
||||
ethernet-switch@11 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
reg = <0x11>;
|
||||
dsa,member = <0 1>;
|
||||
@ -509,92 +514,92 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch1phy1: switch1phy1@1 {
|
||||
switch1phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
switch1phy2: switch1phy2@2 {
|
||||
switch1phy2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
switch1phy3: switch1phy3@3 {
|
||||
switch1phy3: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
switch1phy4: switch1phy4@4 {
|
||||
switch1phy4: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
switch1phy5: switch1phy5@5 {
|
||||
switch1phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
switch1phy6: switch1phy6@6 {
|
||||
switch1phy6: ethernet-phy@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
switch1phy7: switch1phy7@7 {
|
||||
switch1phy7: ethernet-phy@7 {
|
||||
reg = <0x7>;
|
||||
};
|
||||
|
||||
switch1phy8: switch1phy8@8 {
|
||||
switch1phy8: ethernet-phy@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <0x1>;
|
||||
label = "lan9";
|
||||
phy-handle = <&switch1phy1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <0x2>;
|
||||
label = "lan10";
|
||||
phy-handle = <&switch1phy2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <0x3>;
|
||||
label = "lan11";
|
||||
phy-handle = <&switch1phy3>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <0x4>;
|
||||
label = "lan12";
|
||||
phy-handle = <&switch1phy4>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <0x5>;
|
||||
label = "lan13";
|
||||
phy-handle = <&switch1phy5>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
ethernet-port@6 {
|
||||
reg = <0x6>;
|
||||
label = "lan14";
|
||||
phy-handle = <&switch1phy6>;
|
||||
};
|
||||
|
||||
port@7 {
|
||||
ethernet-port@7 {
|
||||
reg = <0x7>;
|
||||
label = "lan15";
|
||||
phy-handle = <&switch1phy7>;
|
||||
};
|
||||
|
||||
port@8 {
|
||||
ethernet-port@8 {
|
||||
reg = <0x8>;
|
||||
label = "lan16";
|
||||
phy-handle = <&switch1phy8>;
|
||||
};
|
||||
|
||||
switch1port9: port@9 {
|
||||
switch1port9: ethernet-port@9 {
|
||||
reg = <0x9>;
|
||||
label = "dsa";
|
||||
phy-mode = "2500base-x";
|
||||
@ -602,7 +607,7 @@
|
||||
link = <&switch0port10>;
|
||||
};
|
||||
|
||||
switch1port10: port@a {
|
||||
switch1port10: ethernet-port@a {
|
||||
reg = <0xa>;
|
||||
label = "dsa";
|
||||
phy-mode = "2500base-x";
|
||||
@ -622,7 +627,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
switch1@2 {
|
||||
ethernet-switch@2 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
reg = <0x2>;
|
||||
dsa,member = <0 1>;
|
||||
@ -634,52 +639,52 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch1phy1_topaz: switch1phy1@11 {
|
||||
switch1phy1_topaz: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
|
||||
switch1phy2_topaz: switch1phy2@12 {
|
||||
switch1phy2_topaz: ethernet-phy@12 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
switch1phy3_topaz: switch1phy3@13 {
|
||||
switch1phy3_topaz: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
|
||||
switch1phy4_topaz: switch1phy4@14 {
|
||||
switch1phy4_topaz: ethernet-phy@14 {
|
||||
reg = <0x14>;
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <0x1>;
|
||||
label = "lan9";
|
||||
phy-handle = <&switch1phy1_topaz>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <0x2>;
|
||||
label = "lan10";
|
||||
phy-handle = <&switch1phy2_topaz>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <0x3>;
|
||||
label = "lan11";
|
||||
phy-handle = <&switch1phy3_topaz>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <0x4>;
|
||||
label = "lan12";
|
||||
phy-handle = <&switch1phy4_topaz>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <0x5>;
|
||||
label = "dsa";
|
||||
phy-mode = "2500base-x";
|
||||
@ -689,7 +694,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
switch2@12 {
|
||||
ethernet-switch@12 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
reg = <0x12>;
|
||||
dsa,member = <0 2>;
|
||||
@ -701,92 +706,92 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch2phy1: switch2phy1@1 {
|
||||
switch2phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
switch2phy2: switch2phy2@2 {
|
||||
switch2phy2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
switch2phy3: switch2phy3@3 {
|
||||
switch2phy3: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
switch2phy4: switch2phy4@4 {
|
||||
switch2phy4: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
switch2phy5: switch2phy5@5 {
|
||||
switch2phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
switch2phy6: switch2phy6@6 {
|
||||
switch2phy6: ethernet-phy@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
switch2phy7: switch2phy7@7 {
|
||||
switch2phy7: ethernet-phy@7 {
|
||||
reg = <0x7>;
|
||||
};
|
||||
|
||||
switch2phy8: switch2phy8@8 {
|
||||
switch2phy8: ethernet-phy@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <0x1>;
|
||||
label = "lan17";
|
||||
phy-handle = <&switch2phy1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <0x2>;
|
||||
label = "lan18";
|
||||
phy-handle = <&switch2phy2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <0x3>;
|
||||
label = "lan19";
|
||||
phy-handle = <&switch2phy3>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <0x4>;
|
||||
label = "lan20";
|
||||
phy-handle = <&switch2phy4>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <0x5>;
|
||||
label = "lan21";
|
||||
phy-handle = <&switch2phy5>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
ethernet-port@6 {
|
||||
reg = <0x6>;
|
||||
label = "lan22";
|
||||
phy-handle = <&switch2phy6>;
|
||||
};
|
||||
|
||||
port@7 {
|
||||
ethernet-port@7 {
|
||||
reg = <0x7>;
|
||||
label = "lan23";
|
||||
phy-handle = <&switch2phy7>;
|
||||
};
|
||||
|
||||
port@8 {
|
||||
ethernet-port@8 {
|
||||
reg = <0x8>;
|
||||
label = "lan24";
|
||||
phy-handle = <&switch2phy8>;
|
||||
};
|
||||
|
||||
switch2port9: port@9 {
|
||||
switch2port9: ethernet-port@9 {
|
||||
reg = <0x9>;
|
||||
label = "dsa";
|
||||
phy-mode = "2500base-x";
|
||||
@ -805,7 +810,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
switch2@2 {
|
||||
ethernet-switch@2 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
reg = <0x2>;
|
||||
dsa,member = <0 2>;
|
||||
@ -817,52 +822,52 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch2phy1_topaz: switch2phy1@11 {
|
||||
switch2phy1_topaz: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
|
||||
switch2phy2_topaz: switch2phy2@12 {
|
||||
switch2phy2_topaz: ethernet-phy@12 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
switch2phy3_topaz: switch2phy3@13 {
|
||||
switch2phy3_topaz: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
|
||||
switch2phy4_topaz: switch2phy4@14 {
|
||||
switch2phy4_topaz: ethernet-phy@14 {
|
||||
reg = <0x14>;
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <0x1>;
|
||||
label = "lan17";
|
||||
phy-handle = <&switch2phy1_topaz>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <0x2>;
|
||||
label = "lan18";
|
||||
phy-handle = <&switch2phy2_topaz>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <0x3>;
|
||||
label = "lan19";
|
||||
phy-handle = <&switch2phy3_topaz>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <0x4>;
|
||||
label = "lan20";
|
||||
phy-handle = <&switch2phy4_topaz>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <0x5>;
|
||||
label = "dsa";
|
||||
phy-mode = "2500base-x";
|
||||
|
||||
@ -301,10 +301,8 @@
|
||||
};
|
||||
|
||||
/* 88E6141 Topaz switch */
|
||||
switch: switch@3 {
|
||||
switch: ethernet-switch@3 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
@ -314,35 +312,35 @@
|
||||
interrupt-parent = <&cp0_gpio1>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
swport1: port@1 {
|
||||
swport1: ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "lan0";
|
||||
phy-handle = <&swphy1>;
|
||||
};
|
||||
|
||||
swport2: port@2 {
|
||||
swport2: ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "lan1";
|
||||
phy-handle = <&swphy2>;
|
||||
};
|
||||
|
||||
swport3: port@3 {
|
||||
swport3: ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "lan2";
|
||||
phy-handle = <&swphy3>;
|
||||
};
|
||||
|
||||
swport4: port@4 {
|
||||
swport4: ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "lan3";
|
||||
phy-handle = <&swphy4>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
label = "cpu";
|
||||
ethernet = <&cp0_eth1>;
|
||||
@ -355,19 +353,19 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
swphy1: swphy1@17 {
|
||||
swphy1: ethernet-phy@17 {
|
||||
reg = <17>;
|
||||
};
|
||||
|
||||
swphy2: swphy2@18 {
|
||||
swphy2: ethernet-phy@18 {
|
||||
reg = <18>;
|
||||
};
|
||||
|
||||
swphy3: swphy3@19 {
|
||||
swphy3: ethernet-phy@19 {
|
||||
reg = <19>;
|
||||
};
|
||||
|
||||
swphy4: swphy4@20 {
|
||||
swphy4: ethernet-phy@20 {
|
||||
reg = <20>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -497,42 +497,42 @@
|
||||
reset-deassert-us = <10000>;
|
||||
};
|
||||
|
||||
switch0: switch0@4 {
|
||||
switch0: ethernet-switch@4 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
reg = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_switch_reset_pins>;
|
||||
reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "lan2";
|
||||
phy-handle = <&switch0phy0>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "lan1";
|
||||
phy-handle = <&switch0phy1>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "lan4";
|
||||
phy-handle = <&switch0phy2>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "lan3";
|
||||
phy-handle = <&switch0phy3>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
label = "cpu";
|
||||
ethernet = <&cp1_eth2>;
|
||||
@ -545,19 +545,19 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0phy0: switch0phy0@11 {
|
||||
switch0phy0: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
|
||||
switch0phy1: switch0phy1@12 {
|
||||
switch0phy1: ethernet-phy@12 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
switch0phy2: switch0phy2@13 {
|
||||
switch0phy2: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
|
||||
switch0phy3: switch0phy3@14 {
|
||||
switch0phy3: ethernet-phy@14 {
|
||||
reg = <0x14>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -207,11 +207,9 @@
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
switch6: switch0@6 {
|
||||
switch6: ethernet-switch@6 {
|
||||
/* Actual device is MV88E6393X */
|
||||
compatible = "marvell,mv88e6190";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
interrupt-parent = <&cp0_gpio1>;
|
||||
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
|
||||
@ -220,59 +218,59 @@
|
||||
|
||||
dsa,member = <0 0>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "p1";
|
||||
phy-handle = <&switch0phy1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "p2";
|
||||
phy-handle = <&switch0phy2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "p3";
|
||||
phy-handle = <&switch0phy3>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "p4";
|
||||
phy-handle = <&switch0phy4>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
label = "p5";
|
||||
phy-handle = <&switch0phy5>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
ethernet-port@6 {
|
||||
reg = <6>;
|
||||
label = "p6";
|
||||
phy-handle = <&switch0phy6>;
|
||||
};
|
||||
|
||||
port@7 {
|
||||
ethernet-port@7 {
|
||||
reg = <7>;
|
||||
label = "p7";
|
||||
phy-handle = <&switch0phy7>;
|
||||
};
|
||||
|
||||
port@8 {
|
||||
ethernet-port@8 {
|
||||
reg = <8>;
|
||||
label = "p8";
|
||||
phy-handle = <&switch0phy8>;
|
||||
};
|
||||
|
||||
port@9 {
|
||||
ethernet-port@9 {
|
||||
reg = <9>;
|
||||
label = "p9";
|
||||
phy-mode = "10gbase-r";
|
||||
@ -280,7 +278,7 @@
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@a {
|
||||
ethernet-port@a {
|
||||
reg = <10>;
|
||||
ethernet = <&cp0_eth0>;
|
||||
phy-mode = "10gbase-r";
|
||||
@ -293,35 +291,35 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0phy1: switch0phy1@1 {
|
||||
switch0phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
switch0phy2: switch0phy2@2 {
|
||||
switch0phy2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
switch0phy3: switch0phy3@3 {
|
||||
switch0phy3: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
switch0phy4: switch0phy4@4 {
|
||||
switch0phy4: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
switch0phy5: switch0phy5@5 {
|
||||
switch0phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
switch0phy6: switch0phy6@6 {
|
||||
switch0phy6: ethernet-phy@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
switch0phy7: switch0phy7@7 {
|
||||
switch0phy7: ethernet-phy@7 {
|
||||
reg = <0x7>;
|
||||
};
|
||||
|
||||
switch0phy8: switch0phy8@8 {
|
||||
switch0phy8: ethernet-phy@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user