From 61249ce08ee9d031070281dbf36871f1c794abb8 Mon Sep 17 00:00:00 2001 From: Jungseung Lee Date: Thu, 2 Apr 2020 21:10:22 +0900 Subject: [PATCH] spi: spi-ep93xx: fix wrong SPI mode selection The mode bits on control register 0 are in a different order compared to the spi mode define values. Thus, in the current code, it fails to set the correct SPI mode selection. Fix it. Signed-off-by: Jungseung Lee Link: https://lore.kernel.org/r/20200402121022.9976-1-js07.lee@samsung.com Signed-off-by: Mark Brown --- drivers/spi/spi-ep93xx.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c index 4e1ccd4e52b6..8c854b187b1d 100644 --- a/drivers/spi/spi-ep93xx.c +++ b/drivers/spi/spi-ep93xx.c @@ -31,7 +31,8 @@ #include #define SSPCR0 0x0000 -#define SSPCR0_MODE_SHIFT 6 +#define SSPCR0_SPO BIT(6) +#define SSPCR0_SPH BIT(7) #define SSPCR0_SCR_SHIFT 8 #define SSPCR1 0x0004 @@ -159,7 +160,10 @@ static int ep93xx_spi_chip_setup(struct spi_master *master, return err; cr0 = div_scr << SSPCR0_SCR_SHIFT; - cr0 |= (spi->mode & (SPI_CPHA | SPI_CPOL)) << SSPCR0_MODE_SHIFT; + if (spi->mode & SPI_CPOL) + cr0 |= SSPCR0_SPO; + if (spi->mode & SPI_CPHA) + cr0 |= SSPCR0_SPH; cr0 |= dss; dev_dbg(&master->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",