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MIPS: define bits introduced for hybrid FPRs
Add definitions for the FRE & UFE bits in Config5, and the FREP bit in FPIR. These bits are used to support a hybrid FPR scheme allowing a mixture of FP32 & FP64 code to execute within a task. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: linux-fsdevel@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7674/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -653,6 +653,8 @@
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#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
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#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
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#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
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#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
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#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
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#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
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#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
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#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
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@ -692,6 +694,7 @@
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#define MIPS_FPIR_W (_ULCAST_(1) << 20)
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#define MIPS_FPIR_L (_ULCAST_(1) << 21)
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#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
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#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
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/*
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* Bits in the MIPS32 Memory Segmentation registers.
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