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This pull request contains the following notable changes:
- add support to new memory parts. - fix of spansion_quad_enable(). - fix of the Candence QSPI driver. - constify some structure instances of the Freescale QSPI driver. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYPBLJAAoJEOfg6AsdGklyuiwQAK+8obDq8ZV2Xt0d1uEuEiWY Trqc3hl6oIuroUuUkaVBjSAvL3kj3u0TdHyZPXiRqikvJjVgPC8Ef9gGvauiL3Bk F1wBiixXAAfoZsEUxkaEjQ9HxAosmf/5vtM6xSKq6T2SbYrbSL/LNP9YvnbKHn6I gupjwEEEb2oLE9MRbNBttq/rTnLZD0xMPmN9qBfVWgXQ6E+rRSjqpmjM1BRPHSt8 v019vv5jKhZWKI/xvTPnDtxp1h9mCk9uxAqHHVaiiNrNP3mdaRE7sSec5Ja+he2S JIpDeM9Dd7UBsPFz49u3ZoLpES5dQg3AL5zugYCWje24xV+hbqdtynKPi+oWCwLH b8bzoanV07A3b732ClOvWSS4fuV1bYvLUs8usAU4qGz4yL2+pexWvwEmnsTy8SOJ l903Lk+FD1vSwTCyqb8Oj/WhlOyChVCD/KirpBhr41W6DDwr2lcur31AufxNfkIS T5+JKRb9+SvOsjNE1WwlJkGbYSr86hnl7gfGY0Co6372xRYM/pFTtGr5gjWMgqpg 9jB8g2afsu4I2rhXVX+Ncj+Ptbdr69u5ErM055PWWOm+VaJb9D56b7ZJxifPAYXL iST3oC3QT47qH3nukRZuGRc6v1gkYSpOVol19QumgB+hneytCeAXDq1p+lAIR15l ekMyjUdZuK/8ywKTn7Oi =jyez -----END PGP SIGNATURE----- Merge tag 'spi-nor/for-4.10' of git://github.com/spi-nor/linux From Cyrille Pitchen: """ This pull request contains the following notable changes: - add support to new memory parts. - fix of spansion_quad_enable(). - fix of the Candence QSPI driver. - constify some structure instances of the Freescale QSPI driver. """
This commit is contained in:
Brian Norris
commit
5fed67df87
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@ -1077,12 +1077,14 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
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/* Get flash device data */
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for_each_available_child_of_node(dev->of_node, np) {
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if (of_property_read_u32(np, "reg", &cs)) {
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ret = of_property_read_u32(np, "reg", &cs);
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if (ret) {
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dev_err(dev, "Couldn't determine chip select.\n");
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goto err;
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}
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if (cs > CQSPI_MAX_CHIPSELECT) {
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if (cs >= CQSPI_MAX_CHIPSELECT) {
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ret = -EINVAL;
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dev_err(dev, "Chip select %d out of range.\n", cs);
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goto err;
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}
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@ -224,7 +224,7 @@ struct fsl_qspi_devtype_data {
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int driver_data;
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};
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static struct fsl_qspi_devtype_data vybrid_data = {
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static const struct fsl_qspi_devtype_data vybrid_data = {
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.devtype = FSL_QUADSPI_VYBRID,
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.rxfifo = 128,
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.txfifo = 64,
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@ -232,7 +232,7 @@ static struct fsl_qspi_devtype_data vybrid_data = {
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.driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
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};
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static struct fsl_qspi_devtype_data imx6sx_data = {
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static const struct fsl_qspi_devtype_data imx6sx_data = {
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.devtype = FSL_QUADSPI_IMX6SX,
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.rxfifo = 128,
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.txfifo = 512,
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@ -241,7 +241,7 @@ static struct fsl_qspi_devtype_data imx6sx_data = {
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| QUADSPI_QUIRK_TKT245618,
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};
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static struct fsl_qspi_devtype_data imx7d_data = {
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static const struct fsl_qspi_devtype_data imx7d_data = {
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.devtype = FSL_QUADSPI_IMX7D,
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.rxfifo = 512,
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.txfifo = 512,
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@ -250,7 +250,7 @@ static struct fsl_qspi_devtype_data imx7d_data = {
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| QUADSPI_QUIRK_4X_INT_CLK,
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};
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static struct fsl_qspi_devtype_data imx6ul_data = {
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static const struct fsl_qspi_devtype_data imx6ul_data = {
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.devtype = FSL_QUADSPI_IMX6UL,
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.rxfifo = 128,
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.txfifo = 512,
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@ -799,6 +799,7 @@ static const struct flash_info spi_nor_ids[] = {
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{ "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
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{ "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
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{ "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
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{ "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
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{ "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
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@ -825,6 +826,7 @@ static const struct flash_info spi_nor_ids[] = {
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/* Everspin */
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{ "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
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{ "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
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{ "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
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/* Fujitsu */
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{ "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
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@ -872,11 +874,13 @@ static const struct flash_info spi_nor_ids[] = {
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{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
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{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
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{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
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{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K) },
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{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
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{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
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{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
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/* Micron */
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{ "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
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{ "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
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{ "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
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{ "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
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@ -905,7 +909,7 @@ static const struct flash_info spi_nor_ids[] = {
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{ "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
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{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
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{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
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{ "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
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{ "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
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@ -921,6 +925,7 @@ static const struct flash_info spi_nor_ids[] = {
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{ "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
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{ "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
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{ "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) },
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{ "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
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/* SST -- large erase sizes are "overlays", "sectors" are 4K */
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{ "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
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@ -1255,6 +1260,13 @@ static int spansion_quad_enable(struct spi_nor *nor)
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return -EINVAL;
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}
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ret = spi_nor_wait_till_ready(nor);
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if (ret) {
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dev_err(nor->dev,
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"timeout while writing configuration register\n");
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return ret;
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}
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/* read back and check it */
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ret = read_cr(nor);
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if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
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