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tty/serial: Fix break handling for PORT_TEGRA
When a break is received, Tegra's UART apparently fills the FIFO with 0 bytes. These must be drained so that they aren't interpreted as actual data received. This allows e.g. MAGIC_SYSRQ to work on Tegra's UARTs. v2: Added FIXME comment to clear_rx_fifo Originally-by: Laxman Dewangan <ldewangan@nvidia.com> Cc: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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@ -1433,6 +1433,27 @@ static void serial8250_enable_ms(struct uart_port *port)
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serial_out(up, UART_IER, up->ier);
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}
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/*
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* Clear the Tegra rx fifo after a break
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*
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* FIXME: This needs to become a port specific callback once we have a
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* framework for this
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*/
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static void clear_rx_fifo(struct uart_8250_port *up)
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{
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unsigned int status, tmout = 10000;
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do {
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status = serial_in(up, UART_LSR);
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if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
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status = serial_in(up, UART_RX);
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else
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break;
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if (--tmout == 0)
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break;
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udelay(1);
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} while (1);
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}
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static void
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receive_chars(struct uart_8250_port *up, unsigned int *status)
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{
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@ -1467,6 +1488,13 @@ receive_chars(struct uart_8250_port *up, unsigned int *status)
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if (lsr & UART_LSR_BI) {
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lsr &= ~(UART_LSR_FE | UART_LSR_PE);
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up->port.icount.brk++;
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/*
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* If tegra port then clear the rx fifo to
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* accept another break/character.
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*/
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if (up->port.type == PORT_TEGRA)
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clear_rx_fifo(up);
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/*
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* We do the SysRQ and SAK checking
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* here because otherwise the break
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@ -119,6 +119,7 @@
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#define UART_MCR_DTR 0x01 /* DTR complement */
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#define UART_LSR 5 /* In: Line Status Register */
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#define UART_LSR_FIFOE 0x80 /* Fifo error */
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#define UART_LSR_TEMT 0x40 /* Transmitter empty */
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#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
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#define UART_LSR_BI 0x10 /* Break interrupt indicator */
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