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phy: qcom-qmp: pcs: Add v6.20 register offsets

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The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for
PCIE g4x2. Add the new PCS offsets in a dedicated header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230208180020.2761766-4-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Abel Vesa 2023-02-08 20:00:12 +02:00 committed by Vinod Koul
parent efecba3c9f
commit 5f70540273
2 changed files with 20 additions and 0 deletions
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18
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h Normal file
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@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2023, Linaro Limited
*/
#ifndef QCOM_PHY_QMP_PCS_V6_20_H_
#define QCOM_PHY_QMP_PCS_V6_20_H_
/* Only for QMP V6_20 PHY - USB/PCIe PCS registers */
#define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178
#define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190
#define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8
#define QPHY_V6_20_PCS_TX_RX_CONFIG1 0x1dc
#define QPHY_V6_20_PCS_TX_RX_CONFIG2 0x1e0
#define QPHY_V6_20_PCS_EQ_CONFIG4 0x1f8
#define QPHY_V6_20_PCS_EQ_CONFIG5 0x1fc
#endif

2
drivers/phy/qualcomm/phy-qcom-qmp.h
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@ -40,6 +40,8 @@
#include "phy-qcom-qmp-pcs-v6.h"
#include "phy-qcom-qmp-pcs-v6_20.h"
/* Only for QMP V3 & V4 PHY - DP COM registers */
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
#define QPHY_V3_DP_COM_SW_RESET 0x04