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drm/arm/malidp:- Define a common list of AFBC format modifiers supported for DP500, DP550 and DP650
We need to define a common list of format modifiers supported by each of the Mali display processors. The following are the constraints with AFBC:- 1. AFBC is not supported for the formats defined in malidp_hw_format_is_linear_only() 2. Some of the formats are supported only with AFBC modifiers. Thus we have introduced a new function 'malidp_hw_format_is_afbc_only()' which verifies the same. 3. AFBC_FORMAT_MOD_YTR needs to be provided for any RGB format. 4. Formats <= 16bpp cannot support AFBC_FORMAT_MOD_SPLIT. 5. CBR should not be set for non-subsampled formats. 6. SMART layer does not support framebuffer with AFBC modifiers. Return -EINVAL for such a scenario. 7. AFBC_FORMAT_MOD_YTR is not supported for any YUV formats. 8. Formats which are subsampled cannot support AFBC_FORMAT_MOD_SPLIT. However in DP550, YUV_420_10BIT is supported with AFBC_FORMAT_MOD_SPLIT. This feature has been identified with MALIDP_DEVICE_AFBC_YUV_420_10_SUPPORT_SPLIT. 9. In DP550 and DP650, for YUYV, the hardware supports different format-ids to be used with and without AFBC modifier. We have used the feature 'MALIDP_DEVICE_AFBC_YUYV_USE_422_P2' to identify this characteristic. 10. DP500 does not support split mode (ie AFBC_FORMAT_MOD_SPLIT). We have used the feature 'MALIDP_DEVICE_AFBC_SUPPORT_SPLIT' to identify the DPs which support SPLIT mode. 11. DP550 supports YUV420 with split mode. We have defined the feature 'AFBC_SUPPORT_SPLIT_WITH_YUV_420_10' to identify this characteristic. Changes since v1:- - Merged https://patchwork.freedesktop.org/patch/265215/ into this patch - As Liviu pointed out in the last patch, we can pull the checks outside of the 'while (*modifiers != DRM_FORMAT_MOD_INVALID)' loop - Rebased Changes since v3 (series): - Added the ack - Rebased on the latest drm-misc-next Signed-off-by: Ayan Kumar halder <ayan.halder@arm.com> Reviewed-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Link: https://patchwork.freedesktop.org/patch/291762/?series=57895&rev=1
This commit is contained in:
Ayan Kumar Halder
Ayan kumar halder
parent
ed893860ee
commit
5e290226b1
@ -264,37 +264,17 @@ static bool
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malidp_verify_afbc_framebuffer_caps(struct drm_device *dev,
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const struct drm_mode_fb_cmd2 *mode_cmd)
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{
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const struct drm_format_info *info;
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if ((mode_cmd->modifier[0] >> 56) != DRM_FORMAT_MOD_VENDOR_ARM) {
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DRM_DEBUG_KMS("Unknown modifier (not Arm)\n");
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if (malidp_format_mod_supported(dev, mode_cmd->pixel_format,
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mode_cmd->modifier[0]) == false)
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return false;
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}
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if (mode_cmd->modifier[0] &
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~DRM_FORMAT_MOD_ARM_AFBC(AFBC_MOD_VALID_BITS)) {
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DRM_DEBUG_KMS("Unsupported modifiers\n");
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return false;
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}
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info = drm_get_format_info(dev, mode_cmd);
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if (!info) {
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DRM_DEBUG_KMS("Unable to get the format information\n");
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return false;
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}
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if (info->num_planes != 1) {
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DRM_DEBUG_KMS("AFBC buffers expect one plane\n");
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return false;
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}
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if (mode_cmd->offsets[0] != 0) {
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DRM_DEBUG_KMS("AFBC buffers' plane offset should be 0\n");
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return false;
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}
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switch (mode_cmd->modifier[0] & AFBC_FORMAT_MOD_BLOCK_SIZE_MASK) {
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case AFBC_FORMAT_MOD_BLOCK_SIZE_16x16:
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switch (mode_cmd->modifier[0] & AFBC_SIZE_MASK) {
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case AFBC_SIZE_16X16:
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if ((mode_cmd->width % 16) || (mode_cmd->height % 16)) {
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DRM_DEBUG_KMS("AFBC buffers must be aligned to 16 pixels\n");
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return false;
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@ -319,8 +299,8 @@ malidp_verify_afbc_framebuffer_size(struct drm_device *dev,
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u32 afbc_superblock_size = 0, afbc_superblock_height = 0;
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u32 afbc_superblock_width = 0, afbc_size = 0;
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switch (mode_cmd->modifier[0] & AFBC_FORMAT_MOD_BLOCK_SIZE_MASK) {
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case AFBC_FORMAT_MOD_BLOCK_SIZE_16x16:
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switch (mode_cmd->modifier[0] & AFBC_SIZE_MASK) {
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case AFBC_SIZE_16X16:
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afbc_superblock_height = 16;
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afbc_superblock_width = 16;
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break;
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@ -90,6 +90,12 @@ struct malidp_crtc_state {
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int malidp_de_planes_init(struct drm_device *drm);
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int malidp_crtc_init(struct drm_device *drm);
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bool malidp_hw_format_is_linear_only(u32 format);
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bool malidp_hw_format_is_afbc_only(u32 format);
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bool malidp_format_mod_supported(struct drm_device *drm,
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u32 format, u64 modifier);
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#ifdef CONFIG_DEBUG_FS
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void malidp_error(struct malidp_drm *malidp,
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struct malidp_error_stats *error_stats, u32 status,
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@ -60,6 +60,8 @@ static const struct malidp_format_id malidp500_de_formats[] = {
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#define MALIDP_ID(__group, __format) \
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((((__group) & 0x7) << 3) | ((__format) & 0x7))
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#define AFBC_YUV_422_FORMAT_ID MALIDP_ID(5, 1)
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#define MALIDP_COMMON_FORMATS \
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/* fourcc, layers supporting the format, internal id */ \
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{ DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | SE_MEMWRITE, MALIDP_ID(0, 0) }, \
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@ -162,6 +164,32 @@ static const struct malidp_layer malidp650_layers[] = {
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ROTATE_NONE, 0 },
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};
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const u64 malidp_format_modifiers[] = {
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/* All RGB formats (except XRGB, RGBX, XBGR, BGRX) */
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DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_YTR | AFBC_SPARSE),
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DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_YTR),
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/* All RGB formats > 16bpp (except XRGB, RGBX, XBGR, BGRX) */
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DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_YTR | AFBC_SPARSE | AFBC_SPLIT),
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/* All 8 or 10 bit YUV 444 formats. */
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/* In DP550, 10 bit YUV 420 format also supported */
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DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_SPARSE | AFBC_SPLIT),
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/* YUV 420, 422 P1 8 bit and YUV 444 8 bit/10 bit formats */
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DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_SPARSE),
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DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16),
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/* YUV 420, 422 P1 8, 10 bit formats */
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DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_CBR | AFBC_SPARSE),
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DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_CBR),
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/* All formats */
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DRM_FORMAT_MOD_LINEAR,
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DRM_FORMAT_MOD_INVALID
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};
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#define SE_N_SCALING_COEFFS 96
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static const u16 dp500_se_scaling_coeffs[][SE_N_SCALING_COEFFS] = {
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[MALIDP_UPSCALING_COEFFS - 1] = {
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@ -866,7 +894,10 @@ const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES] = {
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.se_base = MALIDP550_SE_BASE,
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.dc_base = MALIDP550_DC_BASE,
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.out_depth_base = MALIDP550_DE_OUTPUT_DEPTH,
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.features = MALIDP_REGMAP_HAS_CLEARIRQ,
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.features = MALIDP_REGMAP_HAS_CLEARIRQ |
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MALIDP_DEVICE_AFBC_SUPPORT_SPLIT |
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MALIDP_DEVICE_AFBC_YUV_420_10_SUPPORT_SPLIT |
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MALIDP_DEVICE_AFBC_YUYV_USE_422_P2,
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.n_layers = ARRAY_SIZE(malidp550_layers),
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.layers = malidp550_layers,
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.de_irq_map = {
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@ -912,7 +943,9 @@ const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES] = {
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.se_base = MALIDP550_SE_BASE,
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.dc_base = MALIDP550_DC_BASE,
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.out_depth_base = MALIDP550_DE_OUTPUT_DEPTH,
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.features = MALIDP_REGMAP_HAS_CLEARIRQ,
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.features = MALIDP_REGMAP_HAS_CLEARIRQ |
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MALIDP_DEVICE_AFBC_SUPPORT_SPLIT |
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MALIDP_DEVICE_AFBC_YUYV_USE_422_P2,
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.n_layers = ARRAY_SIZE(malidp650_layers),
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.layers = malidp650_layers,
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.de_irq_map = {
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@ -961,19 +994,72 @@ const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES] = {
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};
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u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,
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u8 layer_id, u32 format)
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u8 layer_id, u32 format, bool has_modifier)
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{
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unsigned int i;
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for (i = 0; i < map->n_pixel_formats; i++) {
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if (((map->pixel_formats[i].layer & layer_id) == layer_id) &&
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(map->pixel_formats[i].format == format))
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return map->pixel_formats[i].id;
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(map->pixel_formats[i].format == format)) {
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/*
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* In some DP550 and DP650, DRM_FORMAT_YUYV + AFBC modifier
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* is supported by a different h/w format id than
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* DRM_FORMAT_YUYV (only).
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*/
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if (format == DRM_FORMAT_YUYV &&
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(has_modifier) &&
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(map->features & MALIDP_DEVICE_AFBC_YUYV_USE_422_P2))
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return AFBC_YUV_422_FORMAT_ID;
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else
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return map->pixel_formats[i].id;
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}
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}
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return MALIDP_INVALID_FORMAT_ID;
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}
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bool malidp_hw_format_is_linear_only(u32 format)
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{
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switch (format) {
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case DRM_FORMAT_ARGB2101010:
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case DRM_FORMAT_RGBA1010102:
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case DRM_FORMAT_BGRA1010102:
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case DRM_FORMAT_ARGB8888:
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case DRM_FORMAT_RGBA8888:
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case DRM_FORMAT_BGRA8888:
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case DRM_FORMAT_XBGR8888:
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_RGBX8888:
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case DRM_FORMAT_BGRX8888:
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case DRM_FORMAT_RGB888:
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case DRM_FORMAT_RGB565:
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case DRM_FORMAT_ARGB1555:
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case DRM_FORMAT_RGBA5551:
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case DRM_FORMAT_BGRA5551:
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case DRM_FORMAT_UYVY:
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case DRM_FORMAT_XYUV8888:
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case DRM_FORMAT_XVYU2101010:
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case DRM_FORMAT_X0L2:
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case DRM_FORMAT_X0L0:
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return true;
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default:
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return false;
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}
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}
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bool malidp_hw_format_is_afbc_only(u32 format)
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{
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switch (format) {
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case DRM_FORMAT_VUY888:
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case DRM_FORMAT_VUY101010:
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case DRM_FORMAT_YUV420_8BIT:
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case DRM_FORMAT_YUV420_10BIT:
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return true;
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default:
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return false;
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}
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}
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static void malidp_hw_clear_irq(struct malidp_hw_device *hwdev, u8 block, u32 irq)
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{
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u32 base = malidp_get_block_base(hwdev, block);
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@ -95,7 +95,10 @@ struct malidp_se_config {
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};
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/* regmap features */
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#define MALIDP_REGMAP_HAS_CLEARIRQ (1 << 0)
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#define MALIDP_REGMAP_HAS_CLEARIRQ BIT(0)
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#define MALIDP_DEVICE_AFBC_SUPPORT_SPLIT BIT(1)
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#define MALIDP_DEVICE_AFBC_YUV_420_10_SUPPORT_SPLIT BIT(2)
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#define MALIDP_DEVICE_AFBC_YUYV_USE_422_P2 BIT(3)
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struct malidp_hw_regmap {
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/* address offset of the DE register bank */
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@ -321,7 +324,7 @@ int malidp_se_irq_init(struct drm_device *drm, int irq);
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void malidp_se_irq_fini(struct malidp_hw_device *hwdev);
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u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,
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u8 layer_id, u32 format);
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u8 layer_id, u32 format, bool has_modifier);
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static inline u8 malidp_hw_get_pitch_align(struct malidp_hw_device *hwdev, bool rotated)
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{
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@ -390,9 +393,18 @@ static inline void malidp_se_set_enh_coeffs(struct malidp_hw_device *hwdev)
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#define MALIDP_GAMMA_LUT_SIZE 4096
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#define AFBC_MOD_VALID_BITS (AFBC_FORMAT_MOD_BLOCK_SIZE_MASK | \
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AFBC_FORMAT_MOD_YTR | AFBC_FORMAT_MOD_SPLIT | \
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AFBC_FORMAT_MOD_SPARSE | AFBC_FORMAT_MOD_CBR | \
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AFBC_FORMAT_MOD_TILED | AFBC_FORMAT_MOD_SC)
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#define AFBC_SIZE_MASK AFBC_FORMAT_MOD_BLOCK_SIZE_MASK
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#define AFBC_SIZE_16X16 AFBC_FORMAT_MOD_BLOCK_SIZE_16x16
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#define AFBC_YTR AFBC_FORMAT_MOD_YTR
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#define AFBC_SPARSE AFBC_FORMAT_MOD_SPARSE
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#define AFBC_CBR AFBC_FORMAT_MOD_CBR
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#define AFBC_SPLIT AFBC_FORMAT_MOD_SPLIT
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#define AFBC_TILED AFBC_FORMAT_MOD_TILED
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#define AFBC_SC AFBC_FORMAT_MOD_SC
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#define AFBC_MOD_VALID_BITS (AFBC_SIZE_MASK | AFBC_YTR | AFBC_SPLIT | \
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AFBC_SPARSE | AFBC_CBR | AFBC_TILED | AFBC_SC)
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extern const u64 malidp_format_modifiers[];
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#endif /* __MALIDP_HW_H__ */
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@ -143,7 +143,7 @@ malidp_mw_encoder_atomic_check(struct drm_encoder *encoder,
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mw_state->format =
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malidp_hw_get_format_id(&malidp->dev->hw->map, SE_MEMWRITE,
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fb->format->format);
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fb->format->format, !!fb->modifier);
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if (mw_state->format == MALIDP_INVALID_FORMAT_ID) {
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struct drm_format_name_buf format_name;
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@ -52,6 +52,8 @@
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#define MALIDP550_LS_ENABLE 0x01c
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#define MALIDP550_LS_R1_IN_SIZE 0x020
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#define MODIFIERS_COUNT_MAX 15
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/*
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* This 4-entry look-up-table is used to determine the full 8-bit alpha value
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* for formats with 1- or 2-bit alpha channels.
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@ -145,6 +147,119 @@ static void malidp_plane_atomic_print_state(struct drm_printer *p,
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drm_printf(p, "\tmmu_prefetch_pgsize=%d\n", ms->mmu_prefetch_pgsize);
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}
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bool malidp_format_mod_supported(struct drm_device *drm,
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u32 format, u64 modifier)
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{
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const struct drm_format_info *info;
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const u64 *modifiers;
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struct malidp_drm *malidp = drm->dev_private;
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const struct malidp_hw_regmap *map = &malidp->dev->hw->map;
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if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
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return false;
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/* Some pixel formats are supported without any modifier */
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if (modifier == DRM_FORMAT_MOD_LINEAR) {
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/*
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* However these pixel formats need to be supported with
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* modifiers only
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*/
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return !malidp_hw_format_is_afbc_only(format);
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}
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if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_ARM) {
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DRM_ERROR("Unknown modifier (not Arm)\n");
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return false;
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}
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if (modifier &
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~DRM_FORMAT_MOD_ARM_AFBC(AFBC_MOD_VALID_BITS)) {
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DRM_DEBUG_KMS("Unsupported modifiers\n");
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return false;
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}
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modifiers = malidp_format_modifiers;
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/* SPLIT buffers must use SPARSE layout */
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if (WARN_ON_ONCE((modifier & AFBC_SPLIT) && !(modifier & AFBC_SPARSE)))
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return false;
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/* CBR only applies to YUV formats, where YTR should be always 0 */
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if (WARN_ON_ONCE((modifier & AFBC_CBR) && (modifier & AFBC_YTR)))
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return false;
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while (*modifiers != DRM_FORMAT_MOD_INVALID) {
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if (*modifiers == modifier)
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break;
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modifiers++;
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}
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/* return false, if the modifier was not found */
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if (*modifiers == DRM_FORMAT_MOD_INVALID) {
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DRM_DEBUG_KMS("Unsupported modifier\n");
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return false;
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}
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info = drm_format_info(format);
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if (info->num_planes != 1) {
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DRM_DEBUG_KMS("AFBC buffers expect one plane\n");
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return false;
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}
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if (malidp_hw_format_is_linear_only(format) == true) {
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DRM_DEBUG_KMS("Given format (0x%x) is supported is linear mode only\n",
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format);
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return false;
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}
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/*
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* RGB formats need to provide YTR modifier and YUV formats should not
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* provide YTR modifier.
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*/
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if (!(info->is_yuv) != !!(modifier & AFBC_FORMAT_MOD_YTR)) {
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DRM_DEBUG_KMS("AFBC_FORMAT_MOD_YTR is %s for %s formats\n",
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info->is_yuv ? "disallowed" : "mandatory",
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info->is_yuv ? "YUV" : "RGB");
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return false;
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}
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if (modifier & AFBC_SPLIT) {
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if (!info->is_yuv) {
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if (drm_format_plane_cpp(format, 0) <= 2) {
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DRM_DEBUG_KMS("RGB formats <= 16bpp are not supported with SPLIT\n");
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return false;
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}
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}
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if ((drm_format_horz_chroma_subsampling(format) != 1) ||
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(drm_format_vert_chroma_subsampling(format) != 1)) {
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if (!(format == DRM_FORMAT_YUV420_10BIT &&
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(map->features & MALIDP_DEVICE_AFBC_YUV_420_10_SUPPORT_SPLIT))) {
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DRM_DEBUG_KMS("Formats which are sub-sampled should never be split\n");
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return false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (modifier & AFBC_CBR) {
|
||||
if ((drm_format_horz_chroma_subsampling(format) == 1) ||
|
||||
(drm_format_vert_chroma_subsampling(format) == 1)) {
|
||||
DRM_DEBUG_KMS("Formats which are not sub-sampled should not have CBR set\n");
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool malidp_format_mod_supported_per_plane(struct drm_plane *plane,
|
||||
u32 format, u64 modifier)
|
||||
{
|
||||
return malidp_format_mod_supported(plane->dev, format, modifier);
|
||||
}
|
||||
|
||||
static const struct drm_plane_funcs malidp_de_plane_funcs = {
|
||||
.update_plane = drm_atomic_helper_update_plane,
|
||||
.disable_plane = drm_atomic_helper_disable_plane,
|
||||
@ -153,6 +268,7 @@ static const struct drm_plane_funcs malidp_de_plane_funcs = {
|
||||
.atomic_duplicate_state = malidp_duplicate_plane_state,
|
||||
.atomic_destroy_state = malidp_destroy_plane_state,
|
||||
.atomic_print_state = malidp_plane_atomic_print_state,
|
||||
.format_mod_supported = malidp_format_mod_supported_per_plane,
|
||||
};
|
||||
|
||||
static int malidp_se_check_scaling(struct malidp_plane *mp,
|
||||
@ -406,8 +522,8 @@ static int malidp_de_plane_check(struct drm_plane *plane,
|
||||
fb = state->fb;
|
||||
|
||||
ms->format = malidp_hw_get_format_id(&mp->hwdev->hw->map,
|
||||
mp->layer->id,
|
||||
fb->format->format);
|
||||
mp->layer->id, fb->format->format,
|
||||
!!fb->modifier);
|
||||
if (ms->format == MALIDP_INVALID_FORMAT_ID)
|
||||
return -EINVAL;
|
||||
|
||||
@ -469,6 +585,12 @@ static int malidp_de_plane_check(struct drm_plane *plane,
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* SMART layer does not support AFBC */
|
||||
if (mp->layer->id == DE_SMART && fb->modifier) {
|
||||
DRM_ERROR("AFBC framebuffer not supported in SMART layer");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ms->rotmem_size = 0;
|
||||
if (state->rotation & MALIDP_ROTATED_MASK) {
|
||||
int val;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user