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drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support. Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
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@ -12,6 +12,7 @@ struct aspeed_gfx {
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struct regmap *scu;
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u32 dac_reg;
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u32 int_clr_reg;
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u32 vga_scratch_reg;
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u32 throd_val;
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u32 scan_line_max;
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@ -61,6 +61,7 @@
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struct aspeed_gfx_config {
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u32 dac_reg; /* DAC register in SCU */
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u32 int_clear_reg; /* Interrupt clear register */
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u32 vga_scratch_reg; /* VGA scratch register in SCU */
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u32 throd_val; /* Default Threshold Seting */
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u32 scan_line_max; /* Max memory size of one scan line */
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@ -68,6 +69,7 @@ struct aspeed_gfx_config {
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static const struct aspeed_gfx_config ast2400_config = {
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.dac_reg = 0x2c,
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.int_clear_reg = 0x60,
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.vga_scratch_reg = 0x50,
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.throd_val = CRT_THROD_LOW(0x1e) | CRT_THROD_HIGH(0x12),
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.scan_line_max = 64,
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@ -75,6 +77,7 @@ static const struct aspeed_gfx_config ast2400_config = {
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static const struct aspeed_gfx_config ast2500_config = {
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.dac_reg = 0x2c,
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.int_clear_reg = 0x60,
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.vga_scratch_reg = 0x50,
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.throd_val = CRT_THROD_LOW(0x24) | CRT_THROD_HIGH(0x3c),
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.scan_line_max = 128,
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@ -120,7 +123,7 @@ static irqreturn_t aspeed_gfx_irq_handler(int irq, void *data)
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if (reg & CRT_CTRL_VERTICAL_INTR_STS) {
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drm_crtc_handle_vblank(&priv->pipe.crtc);
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writel(reg, priv->base + CRT_CTRL1);
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writel(reg, priv->base + priv->int_clr_reg);
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return IRQ_HANDLED;
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}
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@ -148,6 +151,7 @@ static int aspeed_gfx_load(struct drm_device *drm)
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config = match->data;
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priv->dac_reg = config->dac_reg;
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priv->int_clr_reg = config->int_clear_reg;
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priv->vga_scratch_reg = config->vga_scratch_reg;
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priv->throd_val = config->throd_val;
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priv->scan_line_max = config->scan_line_max;
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