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spi: qup: allow block mode to generate multiple transactions
This let's you write more to the SPI bus than 64K-1 which is important if the block size of a SPI device is >= 64K or some other device wants to do something larger. This has the benefit of completely removing spi_message from the spi-qup transactions Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Varadarajan Narayanan
Mark Brown
parent
3b5ea2c981
commit
5dc47fefe1
@ -120,7 +120,7 @@
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#define SPI_NUM_CHIPSELECTS 4
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#define SPI_MAX_DMA_XFER (SZ_64K - 64)
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#define SPI_MAX_XFER (SZ_64K - 64)
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/* high speed mode is when bus rate is greater then 26MHz */
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#define SPI_HS_MIN_RATE 26000000
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@ -149,6 +149,8 @@ struct spi_qup {
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int n_words;
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int tx_bytes;
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int rx_bytes;
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const u8 *tx_buf;
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u8 *rx_buf;
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int qup_v1;
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int mode;
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@ -173,6 +175,12 @@ static inline bool spi_qup_is_dma_xfer(int mode)
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return false;
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}
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/* get's the transaction size length */
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static inline unsigned int spi_qup_len(struct spi_qup *controller)
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{
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return controller->n_words * controller->w_size;
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}
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static inline bool spi_qup_is_valid_state(struct spi_qup *controller)
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{
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u32 opstate = readl_relaxed(controller->base + QUP_STATE);
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@ -225,10 +233,9 @@ static int spi_qup_set_state(struct spi_qup *controller, u32 state)
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return 0;
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}
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static void spi_qup_read_from_fifo(struct spi_qup *controller,
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struct spi_transfer *xfer, u32 num_words)
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static void spi_qup_read_from_fifo(struct spi_qup *controller, u32 num_words)
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{
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u8 *rx_buf = xfer->rx_buf;
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u8 *rx_buf = controller->rx_buf;
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int i, shift, num_bytes;
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u32 word;
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@ -236,8 +243,9 @@ static void spi_qup_read_from_fifo(struct spi_qup *controller,
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word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
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num_bytes = min_t(int, xfer->len - controller->rx_bytes,
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controller->w_size);
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num_bytes = min_t(int, spi_qup_len(controller) -
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controller->rx_bytes,
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controller->w_size);
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if (!rx_buf) {
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controller->rx_bytes += num_bytes;
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@ -258,13 +266,12 @@ static void spi_qup_read_from_fifo(struct spi_qup *controller,
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}
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}
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static void spi_qup_read(struct spi_qup *controller,
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struct spi_transfer *xfer)
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static void spi_qup_read(struct spi_qup *controller)
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{
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u32 remainder, words_per_block, num_words;
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bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
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remainder = DIV_ROUND_UP(xfer->len - controller->rx_bytes,
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remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->rx_bytes,
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controller->w_size);
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words_per_block = controller->in_blk_sz >> 2;
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@ -285,7 +292,7 @@ static void spi_qup_read(struct spi_qup *controller,
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}
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/* read up to the maximum transfer size available */
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spi_qup_read_from_fifo(controller, xfer, num_words);
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spi_qup_read_from_fifo(controller, num_words);
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remainder -= num_words;
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@ -307,18 +314,18 @@ static void spi_qup_read(struct spi_qup *controller,
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}
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static void spi_qup_write_to_fifo(struct spi_qup *controller,
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struct spi_transfer *xfer, u32 num_words)
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static void spi_qup_write_to_fifo(struct spi_qup *controller, u32 num_words)
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{
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const u8 *tx_buf = xfer->tx_buf;
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const u8 *tx_buf = controller->tx_buf;
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int i, num_bytes;
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u32 word, data;
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for (; num_words; num_words--) {
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word = 0;
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num_bytes = min_t(int, xfer->len - controller->tx_bytes,
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controller->w_size);
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num_bytes = min_t(int, spi_qup_len(controller) -
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controller->tx_bytes,
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controller->w_size);
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if (tx_buf)
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for (i = 0; i < num_bytes; i++) {
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data = tx_buf[controller->tx_bytes + i];
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@ -338,13 +345,12 @@ static void spi_qup_dma_done(void *data)
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complete(&qup->done);
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}
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static void spi_qup_write(struct spi_qup *controller,
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struct spi_transfer *xfer)
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static void spi_qup_write(struct spi_qup *controller)
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{
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bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
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u32 remainder, words_per_block, num_words;
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remainder = DIV_ROUND_UP(xfer->len - controller->tx_bytes,
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remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->tx_bytes,
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controller->w_size);
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words_per_block = controller->out_blk_sz >> 2;
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@ -364,7 +370,7 @@ static void spi_qup_write(struct spi_qup *controller,
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num_words = 1;
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}
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spi_qup_write_to_fifo(controller, xfer, num_words);
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spi_qup_write_to_fifo(controller, num_words);
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remainder -= num_words;
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@ -471,36 +477,62 @@ static int spi_qup_do_pio(struct spi_device *spi, struct spi_transfer *xfer,
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{
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struct spi_master *master = spi->master;
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struct spi_qup *qup = spi_master_get_devdata(master);
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int ret;
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int ret, n_words, iterations, offset = 0;
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ret = spi_qup_io_config(spi, xfer);
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if (ret)
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return ret;
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n_words = qup->n_words;
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iterations = n_words / SPI_MAX_XFER; /* round down */
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qup->rx_buf = xfer->rx_buf;
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qup->tx_buf = xfer->tx_buf;
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ret = spi_qup_set_state(qup, QUP_STATE_RUN);
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if (ret) {
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dev_warn(qup->dev, "cannot set RUN state\n");
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return ret;
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}
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do {
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if (iterations)
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qup->n_words = SPI_MAX_XFER;
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else
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qup->n_words = n_words % SPI_MAX_XFER;
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ret = spi_qup_set_state(qup, QUP_STATE_PAUSE);
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if (ret) {
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dev_warn(qup->dev, "cannot set PAUSE state\n");
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return ret;
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}
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if (qup->tx_buf && offset)
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qup->tx_buf = xfer->tx_buf + offset * SPI_MAX_XFER;
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if (qup->mode == QUP_IO_M_MODE_FIFO)
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spi_qup_write(qup, xfer);
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if (qup->rx_buf && offset)
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qup->rx_buf = xfer->rx_buf + offset * SPI_MAX_XFER;
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ret = spi_qup_set_state(qup, QUP_STATE_RUN);
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if (ret) {
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dev_warn(qup->dev, "%s(%d): cannot set RUN state\n",
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__func__, __LINE__);
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return ret;
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}
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/*
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* if the transaction is small enough, we need
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* to fallback to FIFO mode
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*/
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if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32)))
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qup->mode = QUP_IO_M_MODE_FIFO;
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if (!wait_for_completion_timeout(&qup->done, timeout))
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return -ETIMEDOUT;
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ret = spi_qup_io_config(spi, xfer);
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if (ret)
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return ret;
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ret = spi_qup_set_state(qup, QUP_STATE_RUN);
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if (ret) {
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dev_warn(qup->dev, "cannot set RUN state\n");
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return ret;
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}
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ret = spi_qup_set_state(qup, QUP_STATE_PAUSE);
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if (ret) {
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dev_warn(qup->dev, "cannot set PAUSE state\n");
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return ret;
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}
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if (qup->mode == QUP_IO_M_MODE_FIFO)
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spi_qup_write(qup);
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ret = spi_qup_set_state(qup, QUP_STATE_RUN);
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if (ret) {
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dev_warn(qup->dev, "cannot set RUN state\n");
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return ret;
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}
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if (!wait_for_completion_timeout(&qup->done, timeout))
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return -ETIMEDOUT;
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offset++;
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} while (iterations--);
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return 0;
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}
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@ -508,7 +540,6 @@ static int spi_qup_do_pio(struct spi_device *spi, struct spi_transfer *xfer,
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static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
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{
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struct spi_qup *controller = dev_id;
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struct spi_transfer *xfer = controller->xfer;
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u32 opflags, qup_err, spi_err;
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int error = 0;
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@ -545,10 +576,10 @@ static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
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writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
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} else {
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if (opflags & QUP_OP_IN_SERVICE_FLAG)
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spi_qup_read(controller, xfer);
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spi_qup_read(controller);
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if (opflags & QUP_OP_OUT_SERVICE_FLAG)
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spi_qup_write(controller, xfer);
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spi_qup_write(controller);
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}
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if ((opflags & QUP_OP_MAX_INPUT_DONE_FLAG) || error)
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@ -755,7 +786,8 @@ static int spi_qup_transfer_one(struct spi_master *master,
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return ret;
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timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC);
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timeout = DIV_ROUND_UP(xfer->len * 8, timeout);
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timeout = DIV_ROUND_UP(min_t(unsigned long, SPI_MAX_XFER,
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xfer->len) * 8, timeout);
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timeout = 100 * msecs_to_jiffies(timeout);
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reinit_completion(&controller->done);
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@ -969,7 +1001,7 @@ static int spi_qup_probe(struct platform_device *pdev)
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master->dev.of_node = pdev->dev.of_node;
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master->auto_runtime_pm = true;
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master->dma_alignment = dma_get_cache_alignment();
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master->max_dma_len = SPI_MAX_DMA_XFER;
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master->max_dma_len = SPI_MAX_XFER;
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platform_set_drvdata(pdev, master);
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