mirror of
https://github.com/torvalds/linux.git
synced 2024-10-23 05:30:55 +00:00
Renesas DTS updates for v6.12 (take two)
- Add support for Ethernet TSN and PCIe on the R-Car V4H SoC and the
White-Hawk (Single) development board,
- Add display support for the RZ/G2UL SoC and the RZ/G2UL SMARC EVk
board,
- Add I2C support for the RZ/G3S SoC and the RZ/G3S SMARC EVK board,
- Add support for HDMI audio on the RZ/G2L and RZ/G2LC SMARC EVK
boards,
- Add initial support for the RZ/V2H(P) (R9A09G057) SoC and the RZ/V2H
EVK board,
- Miscellaneous fixes and improvements.
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Merge tag 'renesas-dts-for-v6.12-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.12 (take two)
- Add support for Ethernet TSN and PCIe on the R-Car V4H SoC and the
White-Hawk (Single) development board,
- Add display support for the RZ/G2UL SoC and the RZ/G2UL SMARC EVk
board,
- Add I2C support for the RZ/G3S SoC and the RZ/G3S SMARC EVK board,
- Add support for HDMI audio on the RZ/G2L and RZ/G2LC SMARC EVK
boards,
- Add initial support for the RZ/V2H(P) (R9A09G057) SoC and the RZ/V2H
EVK board,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.12-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (34 commits)
arm64: dts: renesas: r8a779h0: Add family fallback for CSISP IP
arm64: dts: renesas: r8a779a0: Add family fallback for CSISP IP
arm64: dts: renesas: r8a779g0: Add family fallback for CSISP IP
arm64: dts: renesas: r8a779h0: Add family fallback for VIN IP
arm64: dts: renesas: r8a779a0: Add family fallback for VIN IP
arm64: dts: renesas: r8a779g0: Add family fallback for VIN IP
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable watchdog
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable OSTM, I2C, and SDHI
arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes
arm64: dts: renesas: r9a09g057: Add SDHI0-SDHI2 nodes
arm64: dts: renesas: r9a09g057: Add RIIC0-RIIC8 nodes
arm64: dts: renesas: r9a09g057: Add OSTM0-OSTM7 nodes
arm64: dts: renesas: Add initial DTS for RZ/V2H EVK board
arm64: dts: renesas: Add initial SoC DTSI for RZ/V2H(P) SoC
dt-bindings: soc: renesas: Document RZ/V2H EVK board
dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG
arm64: dts: renesas: r9a07g043u11-smarc: Enable DU
arm64: dts: renesas: rzg2lc-smarc: Enable HDMI audio
arm64: dts: renesas: rzg2l-smarc: Enable HDMI audio
arm64: dts: renesas: r9a07g043u: Add DU node
...
Link: https://lore.kernel.org/r/cover.1725374275.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
5d9e36498b
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|
@ -0,0 +1,80 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
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maintainers:
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- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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description:
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On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
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and control of clock signals for the IP modules, generation and control of resets,
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and control over booting, low power consumption and power supply domains.
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properties:
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compatible:
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const: renesas,r9a09g057-cpg
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reg:
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maxItems: 1
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clocks:
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items:
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- description: AUDIO_EXTAL clock input
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- description: RTXIN clock input
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- description: QEXTAL clock input
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clock-names:
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items:
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- const: audio_extal
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- const: rtxin
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- const: qextal
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'#clock-cells':
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description: |
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- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
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and a core clock reference, as defined in
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<dt-bindings/clock/renesas,r9a09g057-cpg.h>,
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- For module clocks, the two clock specifier cells must be "CPG_MOD" and
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a module number. The module number is calculated as the CLKON register
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offset index multiplied by 16, plus the actual bit in the register
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used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the
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calculation is (1 * 16 + 3) = 0x13.
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const: 2
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'#power-domain-cells':
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const: 0
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'#reset-cells':
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description:
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The single reset specifier cell must be the reset number. The reset number
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is calculated as the reset register offset index multiplied by 16, plus the
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actual bit in the register used to reset the specific IP block. For example,
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for SYS_0_PRESETN, the calculation is (3 * 16 + 0) = 0x30.
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#power-domain-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@10420000 {
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compatible = "renesas,r9a09g057-cpg";
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reg = <0x10420000 0x10000>;
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clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
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clock-names = "audio_extal", "rtxin", "qextal";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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@ -527,6 +527,8 @@ properties:
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- description: RZ/V2H(P) (R9A09G057)
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items:
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- enum:
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- renesas,rzv2h-evk # RZ/V2H EVK
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- enum:
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- renesas,r9a09g057h41 # RZ/V2H
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- renesas,r9a09g057h42 # RZ/V2H with Mali-G31 support
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|
|
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@ -112,9 +112,12 @@ dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs-panel-aa104xd12.dtb
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dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb
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dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-cru-csi-ov5645.dtbo
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dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-du-adv7513.dtbo
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dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043-smarc-pmod.dtbo
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r9a07g043u11-smarc-cru-csi-ov5645-dtbs := r9a07g043u11-smarc.dtb r9a07g043u11-smarc-cru-csi-ov5645.dtbo
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dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-cru-csi-ov5645.dtb
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r9a07g043u11-smarc-du-adv7513-dtbs := r9a07g043u11-smarc.dtb r9a07g043u11-smarc-du-adv7513.dtbo
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dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-du-adv7513.dtb
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r9a07g043u11-smarc-pmod-dtbs := r9a07g043u11-smarc.dtb r9a07g043-smarc-pmod.dtbo
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dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-pmod.dtb
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|
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@ -137,5 +140,7 @@ dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb
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|||
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dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
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dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk.dtb
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dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo
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dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo
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|
|
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|||
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@ -1174,7 +1174,8 @@
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};
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vin00: video@e6ef0000 {
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compatible = "renesas,vin-r8a779a0";
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compatible = "renesas,vin-r8a779a0",
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||||
"renesas,rcar-gen4-vin";
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reg = <0 0xe6ef0000 0 0x1000>;
|
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 730>;
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|
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@ -1202,7 +1203,8 @@
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|||
};
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vin01: video@e6ef1000 {
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compatible = "renesas,vin-r8a779a0";
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compatible = "renesas,vin-r8a779a0",
|
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"renesas,rcar-gen4-vin";
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reg = <0 0xe6ef1000 0 0x1000>;
|
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interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
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clocks = <&cpg CPG_MOD 731>;
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|
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@ -1230,7 +1232,8 @@
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|||
};
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vin02: video@e6ef2000 {
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compatible = "renesas,vin-r8a779a0";
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compatible = "renesas,vin-r8a779a0",
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"renesas,rcar-gen4-vin";
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reg = <0 0xe6ef2000 0 0x1000>;
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interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 800>;
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|
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@ -1258,7 +1261,8 @@
|
|||
};
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vin03: video@e6ef3000 {
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compatible = "renesas,vin-r8a779a0";
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compatible = "renesas,vin-r8a779a0",
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"renesas,rcar-gen4-vin";
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reg = <0 0xe6ef3000 0 0x1000>;
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interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 801>;
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@ -1286,7 +1290,8 @@
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};
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vin04: video@e6ef4000 {
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compatible = "renesas,vin-r8a779a0";
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compatible = "renesas,vin-r8a779a0",
|
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"renesas,rcar-gen4-vin";
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reg = <0 0xe6ef4000 0 0x1000>;
|
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 802>;
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|
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@ -1314,7 +1319,8 @@
|
|||
};
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vin05: video@e6ef5000 {
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compatible = "renesas,vin-r8a779a0";
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compatible = "renesas,vin-r8a779a0",
|
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"renesas,rcar-gen4-vin";
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reg = <0 0xe6ef5000 0 0x1000>;
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interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 803>;
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|
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@ -1342,7 +1348,8 @@
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};
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vin06: video@e6ef6000 {
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compatible = "renesas,vin-r8a779a0";
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compatible = "renesas,vin-r8a779a0",
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"renesas,rcar-gen4-vin";
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reg = <0 0xe6ef6000 0 0x1000>;
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interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 804>;
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|
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@ -1370,7 +1377,8 @@
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};
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vin07: video@e6ef7000 {
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compatible = "renesas,vin-r8a779a0";
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compatible = "renesas,vin-r8a779a0",
|
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"renesas,rcar-gen4-vin";
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reg = <0 0xe6ef7000 0 0x1000>;
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interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 805>;
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|
|
@ -1398,7 +1406,8 @@
|
|||
};
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||||
|
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vin08: video@e6ef8000 {
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compatible = "renesas,vin-r8a779a0";
|
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compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef8000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 806>;
|
||||
|
|
@ -1426,7 +1435,8 @@
|
|||
};
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||||
|
||||
vin09: video@e6ef9000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef9000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 807>;
|
||||
|
|
@ -1454,7 +1464,8 @@
|
|||
};
|
||||
|
||||
vin10: video@e6efa000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6efa000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 808>;
|
||||
|
|
@ -1482,7 +1493,8 @@
|
|||
};
|
||||
|
||||
vin11: video@e6efb000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6efb000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 809>;
|
||||
|
|
@ -1510,7 +1522,8 @@
|
|||
};
|
||||
|
||||
vin12: video@e6efc000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6efc000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 810>;
|
||||
|
|
@ -1538,7 +1551,8 @@
|
|||
};
|
||||
|
||||
vin13: video@e6efd000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6efd000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 811>;
|
||||
|
|
@ -1566,7 +1580,8 @@
|
|||
};
|
||||
|
||||
vin14: video@e6efe000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6efe000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
|
|
@ -1594,7 +1609,8 @@
|
|||
};
|
||||
|
||||
vin15: video@e6eff000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6eff000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 813>;
|
||||
|
|
@ -1622,7 +1638,8 @@
|
|||
};
|
||||
|
||||
vin16: video@e6ed0000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ed0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 814>;
|
||||
|
|
@ -1650,7 +1667,8 @@
|
|||
};
|
||||
|
||||
vin17: video@e6ed1000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ed1000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 815>;
|
||||
|
|
@ -1678,7 +1696,8 @@
|
|||
};
|
||||
|
||||
vin18: video@e6ed2000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ed2000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 816>;
|
||||
|
|
@ -1706,7 +1725,8 @@
|
|||
};
|
||||
|
||||
vin19: video@e6ed3000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ed3000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 817>;
|
||||
|
|
@ -1734,7 +1754,8 @@
|
|||
};
|
||||
|
||||
vin20: video@e6ed4000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ed4000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 818>;
|
||||
|
|
@ -1762,7 +1783,8 @@
|
|||
};
|
||||
|
||||
vin21: video@e6ed5000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ed5000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 819>;
|
||||
|
|
@ -1790,7 +1812,8 @@
|
|||
};
|
||||
|
||||
vin22: video@e6ed6000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ed6000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 820>;
|
||||
|
|
@ -1818,7 +1841,8 @@
|
|||
};
|
||||
|
||||
vin23: video@e6ed7000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ed7000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 821>;
|
||||
|
|
@ -1846,7 +1870,8 @@
|
|||
};
|
||||
|
||||
vin24: video@e6ed8000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ed8000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 822>;
|
||||
|
|
@ -1874,7 +1899,8 @@
|
|||
};
|
||||
|
||||
vin25: video@e6ed9000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ed9000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 823>;
|
||||
|
|
@ -1902,7 +1928,8 @@
|
|||
};
|
||||
|
||||
vin26: video@e6eda000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6eda000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 824>;
|
||||
|
|
@ -1930,7 +1957,8 @@
|
|||
};
|
||||
|
||||
vin27: video@e6edb000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6edb000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 825>;
|
||||
|
|
@ -1958,7 +1986,8 @@
|
|||
};
|
||||
|
||||
vin28: video@e6edc000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6edc000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 826>;
|
||||
|
|
@ -1986,7 +2015,8 @@
|
|||
};
|
||||
|
||||
vin29: video@e6edd000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6edd000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 827>;
|
||||
|
|
@ -2014,7 +2044,8 @@
|
|||
};
|
||||
|
||||
vin30: video@e6ede000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ede000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 828>;
|
||||
|
|
@ -2042,7 +2073,8 @@
|
|||
};
|
||||
|
||||
vin31: video@e6edf000 {
|
||||
compatible = "renesas,vin-r8a779a0";
|
||||
compatible = "renesas,vin-r8a779a0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6edf000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 829>;
|
||||
|
|
@ -2469,7 +2501,8 @@
|
|||
};
|
||||
|
||||
isp0: isp@fed00000 {
|
||||
compatible = "renesas,r8a779a0-isp";
|
||||
compatible = "renesas,r8a779a0-isp",
|
||||
"renesas,rcar-gen4-isp";
|
||||
reg = <0 0xfed00000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 612>;
|
||||
|
|
@ -2552,7 +2585,8 @@
|
|||
};
|
||||
|
||||
isp1: isp@fed20000 {
|
||||
compatible = "renesas,r8a779a0-isp";
|
||||
compatible = "renesas,r8a779a0-isp",
|
||||
"renesas,rcar-gen4-isp";
|
||||
reg = <0 0xfed20000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 613>;
|
||||
|
|
@ -2635,7 +2669,8 @@
|
|||
};
|
||||
|
||||
isp2: isp@fed30000 {
|
||||
compatible = "renesas,r8a779a0-isp";
|
||||
compatible = "renesas,r8a779a0-isp",
|
||||
"renesas,rcar-gen4-isp";
|
||||
reg = <0 0xfed30000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 614>;
|
||||
|
|
@ -2718,7 +2753,8 @@
|
|||
};
|
||||
|
||||
isp3: isp@fed40000 {
|
||||
compatible = "renesas,r8a779a0-isp";
|
||||
compatible = "renesas,r8a779a0-isp",
|
||||
"renesas,rcar-gen4-isp";
|
||||
reg = <0 0xfed40000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 615>;
|
||||
|
|
|
|||
|
|
@ -175,6 +175,20 @@
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
pcie0_clkref: pcie0-clkref {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
pcie1_clkref: pcie1-clkref {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
pmu_a76 {
|
||||
compatible = "arm,cortex-a76-pmu";
|
||||
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
|
@ -553,6 +567,20 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
tsn0: ethernet@e6460000 {
|
||||
compatible = "renesas,r8a779g0-ethertsn", "renesas,rcar-gen4-ethertsn";
|
||||
reg = <0 0xe6460000 0 0x7000>,
|
||||
<0 0xe6449000 0 0x500>;
|
||||
reg-names = "tsnes", "gptp";
|
||||
interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
clocks = <&cpg CPG_MOD 2723>;
|
||||
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 2723>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
compatible = "renesas,i2c-r8a779g0",
|
||||
"renesas,rcar-gen4-i2c";
|
||||
|
|
@ -723,6 +751,126 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pciec0: pcie@e65d0000 {
|
||||
compatible = "renesas,r8a779g0-pcie",
|
||||
"renesas,rcar-gen4-pcie";
|
||||
reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
|
||||
<0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
|
||||
<0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
|
||||
<0 0xfe000000 0 0x400000>;
|
||||
reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
|
||||
interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi", "dma", "sft_ce", "app";
|
||||
clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
|
||||
clock-names = "core", "ref";
|
||||
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 624>;
|
||||
reset-names = "pwr";
|
||||
max-link-speed = <4>;
|
||||
num-lanes = <2>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x00 0xff>;
|
||||
device_type = "pci";
|
||||
ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
|
||||
<0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
|
||||
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
|
||||
snps,enable-cdm-check;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pciec1: pcie@e65d8000 {
|
||||
compatible = "renesas,r8a779g0-pcie",
|
||||
"renesas,rcar-gen4-pcie";
|
||||
reg = <0 0xe65d8000 0 0x1000>, <0 0xe65da000 0 0x0800>,
|
||||
<0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
|
||||
<0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
|
||||
<0 0xee900000 0 0x400000>;
|
||||
reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
|
||||
interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi", "dma", "sft_ce", "app";
|
||||
clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
|
||||
clock-names = "core", "ref";
|
||||
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 625>;
|
||||
reset-names = "pwr";
|
||||
max-link-speed = <4>;
|
||||
num-lanes = <2>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x00 0xff>;
|
||||
device_type = "pci";
|
||||
ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00400000>,
|
||||
<0x02000000 0 0xc0000000 0 0xc0000000 0 0x10000000>;
|
||||
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
|
||||
snps,enable-cdm-check;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pciec0_ep: pcie-ep@e65d0000 {
|
||||
compatible = "renesas,r8a779g0-pcie-ep",
|
||||
"renesas,rcar-gen4-pcie-ep";
|
||||
reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
|
||||
<0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
|
||||
<0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
|
||||
<0 0xfe000000 0 0x400000>;
|
||||
reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
|
||||
interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "dma", "sft_ce", "app";
|
||||
clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
|
||||
clock-names = "core", "ref";
|
||||
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 624>;
|
||||
reset-names = "pwr";
|
||||
max-link-speed = <4>;
|
||||
num-lanes = <2>;
|
||||
max-functions = /bits/ 8 <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pciec1_ep: pcie-ep@e65d8000 {
|
||||
compatible = "renesas,r8a779g0-pcie-ep",
|
||||
"renesas,rcar-gen4-pcie-ep";
|
||||
reg = <0 0xe65d8000 0 0x2000>, <0 0xe65da000 0 0x1000>,
|
||||
<0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
|
||||
<0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
|
||||
<0 0xee900000 0 0x400000>;
|
||||
reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
|
||||
interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "dma", "sft_ce", "app";
|
||||
clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
|
||||
clock-names = "core", "ref";
|
||||
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 625>;
|
||||
reset-names = "pwr";
|
||||
max-link-speed = <4>;
|
||||
num-lanes = <2>;
|
||||
max-functions = /bits/ 8 <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
canfd: can@e6660000 {
|
||||
compatible = "renesas,r8a779g0-canfd",
|
||||
"renesas,rcar-gen4-canfd";
|
||||
|
|
@ -1187,7 +1335,8 @@
|
|||
};
|
||||
|
||||
vin00: video@e6ef0000 {
|
||||
compatible = "renesas,vin-r8a779g0";
|
||||
compatible = "renesas,vin-r8a779g0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 730>;
|
||||
|
|
@ -1215,7 +1364,8 @@
|
|||
};
|
||||
|
||||
vin01: video@e6ef1000 {
|
||||
compatible = "renesas,vin-r8a779g0";
|
||||
compatible = "renesas,vin-r8a779g0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef1000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 731>;
|
||||
|
|
@ -1243,7 +1393,8 @@
|
|||
};
|
||||
|
||||
vin02: video@e6ef2000 {
|
||||
compatible = "renesas,vin-r8a779g0";
|
||||
compatible = "renesas,vin-r8a779g0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef2000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 800>;
|
||||
|
|
@ -1271,7 +1422,8 @@
|
|||
};
|
||||
|
||||
vin03: video@e6ef3000 {
|
||||
compatible = "renesas,vin-r8a779g0";
|
||||
compatible = "renesas,vin-r8a779g0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef3000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 801>;
|
||||
|
|
@ -1299,7 +1451,8 @@
|
|||
};
|
||||
|
||||
vin04: video@e6ef4000 {
|
||||
compatible = "renesas,vin-r8a779g0";
|
||||
compatible = "renesas,vin-r8a779g0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef4000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 802>;
|
||||
|
|
@ -1327,7 +1480,8 @@
|
|||
};
|
||||
|
||||
vin05: video@e6ef5000 {
|
||||
compatible = "renesas,vin-r8a779g0";
|
||||
compatible = "renesas,vin-r8a779g0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef5000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 803>;
|
||||
|
|
@ -1355,7 +1509,8 @@
|
|||
};
|
||||
|
||||
vin06: video@e6ef6000 {
|
||||
compatible = "renesas,vin-r8a779g0";
|
||||
compatible = "renesas,vin-r8a779g0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef6000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 804>;
|
||||
|
|
@ -1383,7 +1538,8 @@
|
|||
};
|
||||
|
||||
vin07: video@e6ef7000 {
|
||||
compatible = "renesas,vin-r8a779g0";
|
||||
compatible = "renesas,vin-r8a779g0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef7000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 805>;
|
||||
|
|
@ -1411,7 +1567,8 @@
|
|||
};
|
||||
|
||||
vin08: video@e6ef8000 {
|
||||
compatible = "renesas,vin-r8a779g0";
|
||||
compatible = "renesas,vin-r8a779g0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef8000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 806>;
|
||||
|
|
@ -1439,7 +1596,8 @@
|
|||
};
|
||||
|
||||
vin09: video@e6ef9000 {
|
||||
compatible = "renesas,vin-r8a779g0";
|
||||
compatible = "renesas,vin-r8a779g0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef9000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 807>;
|
||||
|
|
@ -1467,7 +1625,8 @@
|
|||
};
|
||||
|
||||
vin10: video@e6efa000 {
|
||||
compatible = "renesas,vin-r8a779g0";
|
||||
compatible = "renesas,vin-r8a779g0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6efa000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 808>;
|
||||
|
|
@ -1495,7 +1654,8 @@
|
|||
};
|
||||
|
||||
vin11: video@e6efb000 {
|
||||
compatible = "renesas,vin-r8a779g0";
|
||||
compatible = "renesas,vin-r8a779g0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6efb000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 809>;
|
||||
|
|
@ -1523,7 +1683,8 @@
|
|||
};
|
||||
|
||||
vin12: video@e6efc000 {
|
||||
compatible = "renesas,vin-r8a779g0";
|
||||
compatible = "renesas,vin-r8a779g0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6efc000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 810>;
|
||||
|
|
@ -1551,7 +1712,8 @@
|
|||
};
|
||||
|
||||
vin13: video@e6efd000 {
|
||||
compatible = "renesas,vin-r8a779g0";
|
||||
compatible = "renesas,vin-r8a779g0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6efd000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 811>;
|
||||
|
|
@ -1579,7 +1741,8 @@
|
|||
};
|
||||
|
||||
vin14: video@e6efe000 {
|
||||
compatible = "renesas,vin-r8a779g0";
|
||||
compatible = "renesas,vin-r8a779g0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6efe000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
|
|
@ -1607,7 +1770,8 @@
|
|||
};
|
||||
|
||||
vin15: video@e6eff000 {
|
||||
compatible = "renesas,vin-r8a779g0";
|
||||
compatible = "renesas,vin-r8a779g0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6eff000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 813>;
|
||||
|
|
@ -2059,7 +2223,8 @@
|
|||
};
|
||||
|
||||
isp0: isp@fed00000 {
|
||||
compatible = "renesas,r8a779g0-isp";
|
||||
compatible = "renesas,r8a779g0-isp",
|
||||
"renesas,rcar-gen4-isp";
|
||||
reg = <0 0xfed00000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&cpg CPG_MOD 612>;
|
||||
|
|
@ -2142,7 +2307,8 @@
|
|||
};
|
||||
|
||||
isp1: isp@fed20000 {
|
||||
compatible = "renesas,r8a779g0-isp";
|
||||
compatible = "renesas,r8a779g0-isp",
|
||||
"renesas,rcar-gen4-isp";
|
||||
reg = <0 0xfed20000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&cpg CPG_MOD 613>;
|
||||
|
|
|
|||
|
|
@ -24,3 +24,54 @@
|
|||
groups = "hscif0_data", "hscif0_ctrl";
|
||||
function = "hscif0";
|
||||
};
|
||||
|
||||
&pfc {
|
||||
tsn0_pins: tsn0 {
|
||||
mux {
|
||||
groups = "tsn0_link", "tsn0_mdio", "tsn0_rgmii",
|
||||
"tsn0_txcrefclk";
|
||||
function = "tsn0";
|
||||
};
|
||||
|
||||
link {
|
||||
groups = "tsn0_link";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mdio {
|
||||
groups = "tsn0_mdio";
|
||||
drive-strength = <24>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
rgmii {
|
||||
groups = "tsn0_rgmii";
|
||||
drive-strength = <24>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tsn0 {
|
||||
pinctrl-0 = <&tsn0_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy3>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
|
||||
reset-post-delay-us = <4000>;
|
||||
|
||||
phy3: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id002b.0980",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1039,7 +1039,8 @@
|
|||
};
|
||||
|
||||
vin00: video@e6ef0000 {
|
||||
compatible = "renesas,vin-r8a779h0";
|
||||
compatible = "renesas,vin-r8a779h0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 730>;
|
||||
|
|
@ -1067,7 +1068,8 @@
|
|||
};
|
||||
|
||||
vin01: video@e6ef1000 {
|
||||
compatible = "renesas,vin-r8a779h0";
|
||||
compatible = "renesas,vin-r8a779h0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef1000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 731>;
|
||||
|
|
@ -1095,7 +1097,8 @@
|
|||
};
|
||||
|
||||
vin02: video@e6ef2000 {
|
||||
compatible = "renesas,vin-r8a779h0";
|
||||
compatible = "renesas,vin-r8a779h0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef2000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 800>;
|
||||
|
|
@ -1123,7 +1126,8 @@
|
|||
};
|
||||
|
||||
vin03: video@e6ef3000 {
|
||||
compatible = "renesas,vin-r8a779h0";
|
||||
compatible = "renesas,vin-r8a779h0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef3000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 801>;
|
||||
|
|
@ -1151,7 +1155,8 @@
|
|||
};
|
||||
|
||||
vin04: video@e6ef4000 {
|
||||
compatible = "renesas,vin-r8a779h0";
|
||||
compatible = "renesas,vin-r8a779h0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef4000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 802>;
|
||||
|
|
@ -1179,7 +1184,8 @@
|
|||
};
|
||||
|
||||
vin05: video@e6ef5000 {
|
||||
compatible = "renesas,vin-r8a779h0";
|
||||
compatible = "renesas,vin-r8a779h0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef5000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 803>;
|
||||
|
|
@ -1207,7 +1213,8 @@
|
|||
};
|
||||
|
||||
vin06: video@e6ef6000 {
|
||||
compatible = "renesas,vin-r8a779h0";
|
||||
compatible = "renesas,vin-r8a779h0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef6000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 804>;
|
||||
|
|
@ -1235,7 +1242,8 @@
|
|||
};
|
||||
|
||||
vin07: video@e6ef7000 {
|
||||
compatible = "renesas,vin-r8a779h0";
|
||||
compatible = "renesas,vin-r8a779h0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef7000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 805>;
|
||||
|
|
@ -1263,7 +1271,8 @@
|
|||
};
|
||||
|
||||
vin08: video@e6ef8000 {
|
||||
compatible = "renesas,vin-r8a779h0";
|
||||
compatible = "renesas,vin-r8a779h0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef8000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 806>;
|
||||
|
|
@ -1291,7 +1300,8 @@
|
|||
};
|
||||
|
||||
vin09: video@e6ef9000 {
|
||||
compatible = "renesas,vin-r8a779h0";
|
||||
compatible = "renesas,vin-r8a779h0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6ef9000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 807>;
|
||||
|
|
@ -1319,7 +1329,8 @@
|
|||
};
|
||||
|
||||
vin10: video@e6efa000 {
|
||||
compatible = "renesas,vin-r8a779h0";
|
||||
compatible = "renesas,vin-r8a779h0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6efa000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 808>;
|
||||
|
|
@ -1347,7 +1358,8 @@
|
|||
};
|
||||
|
||||
vin11: video@e6efb000 {
|
||||
compatible = "renesas,vin-r8a779h0";
|
||||
compatible = "renesas,vin-r8a779h0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6efb000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 809>;
|
||||
|
|
@ -1375,7 +1387,8 @@
|
|||
};
|
||||
|
||||
vin12: video@e6efc000 {
|
||||
compatible = "renesas,vin-r8a779h0";
|
||||
compatible = "renesas,vin-r8a779h0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6efc000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 810>;
|
||||
|
|
@ -1403,7 +1416,8 @@
|
|||
};
|
||||
|
||||
vin13: video@e6efd000 {
|
||||
compatible = "renesas,vin-r8a779h0";
|
||||
compatible = "renesas,vin-r8a779h0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6efd000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 811>;
|
||||
|
|
@ -1431,7 +1445,8 @@
|
|||
};
|
||||
|
||||
vin14: video@e6efe000 {
|
||||
compatible = "renesas,vin-r8a779h0";
|
||||
compatible = "renesas,vin-r8a779h0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6efe000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
|
|
@ -1459,7 +1474,8 @@
|
|||
};
|
||||
|
||||
vin15: video@e6eff000 {
|
||||
compatible = "renesas,vin-r8a779h0";
|
||||
compatible = "renesas,vin-r8a779h0",
|
||||
"renesas,rcar-gen4-vin";
|
||||
reg = <0 0xe6eff000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 813>;
|
||||
|
|
@ -1813,7 +1829,8 @@
|
|||
};
|
||||
|
||||
isp0: isp@fed00000 {
|
||||
compatible = "renesas,r8a779h0-isp";
|
||||
compatible = "renesas,r8a779h0-isp",
|
||||
"renesas,rcar-gen4-isp";
|
||||
reg = <0 0xfed00000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&cpg CPG_MOD 612>;
|
||||
|
|
@ -1896,7 +1913,8 @@
|
|||
};
|
||||
|
||||
isp1: isp@fed20000 {
|
||||
compatible = "renesas,r8a779h0-isp";
|
||||
compatible = "renesas,r8a779h0-isp",
|
||||
"renesas,rcar-gen4-isp";
|
||||
reg = <0 0xfed20000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&cpg CPG_MOD 613>;
|
||||
|
|
|
|||
|
|
@ -725,6 +725,10 @@
|
|||
power-domains = <&cpg>;
|
||||
#reset-cells = <1>;
|
||||
status = "disabled";
|
||||
|
||||
usb0_vbus_otg: regulator-vbus {
|
||||
regulator-name = "vbus";
|
||||
};
|
||||
};
|
||||
|
||||
ohci0: usb@11c50000 {
|
||||
|
|
|
|||
|
|
@ -129,6 +129,55 @@
|
|||
};
|
||||
};
|
||||
|
||||
vspd: vsp@10870000 {
|
||||
compatible = "renesas,r9a07g043u-vsp2", "renesas,r9a07g044-vsp2";
|
||||
reg = <0 0x10870000 0 0x10000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(149) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>,
|
||||
<&cpg CPG_MOD R9A07G043_LCDC_CLK_P>,
|
||||
<&cpg CPG_MOD R9A07G043_LCDC_CLK_D>;
|
||||
clock-names = "aclk", "pclk", "vclk";
|
||||
power-domains = <&cpg>;
|
||||
resets = <&cpg R9A07G043_LCDC_RESET_N>;
|
||||
renesas,fcp = <&fcpvd>;
|
||||
};
|
||||
|
||||
fcpvd: fcp@10880000 {
|
||||
compatible = "renesas,r9a07g043u-fcpvd", "renesas,fcpv";
|
||||
reg = <0 0x10880000 0 0x10000>;
|
||||
clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>,
|
||||
<&cpg CPG_MOD R9A07G043_LCDC_CLK_P>,
|
||||
<&cpg CPG_MOD R9A07G043_LCDC_CLK_D>;
|
||||
clock-names = "aclk", "pclk", "vclk";
|
||||
power-domains = <&cpg>;
|
||||
resets = <&cpg R9A07G043_LCDC_RESET_N>;
|
||||
};
|
||||
|
||||
du: display@10890000 {
|
||||
compatible = "renesas,r9a07g043u-du";
|
||||
reg = <0 0x10890000 0 0x10000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(152) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>,
|
||||
<&cpg CPG_MOD R9A07G043_LCDC_CLK_P>,
|
||||
<&cpg CPG_MOD R9A07G043_LCDC_CLK_D>;
|
||||
clock-names = "aclk", "pclk", "vclk";
|
||||
power-domains = <&cpg>;
|
||||
resets = <&cpg R9A07G043_LCDC_RESET_N>;
|
||||
renesas,vsps = <&vspd 0>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
irqc: interrupt-controller@110a0000 {
|
||||
compatible = "renesas,r9a07g043u-irqc",
|
||||
"renesas,rzg2l-irqc";
|
||||
|
|
@ -210,8 +259,8 @@
|
|||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x11900000 0 0x40000>,
|
||||
<0x0 0x11940000 0 0x60000>;
|
||||
reg = <0x0 0x11900000 0 0x20000>,
|
||||
<0x0 0x11940000 0 0x40000>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,62 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree overlay for the RZ/G2UL SMARC EVK with ADV7513 transmitter
|
||||
* connected to DU enabled.
|
||||
*
|
||||
* Copyright (C) 2024 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
|
||||
|
||||
#define ADV7513_PARENT_I2C i2c1
|
||||
#include "rz-smarc-du-adv7513.dtsi"
|
||||
|
||||
&pinctrl {
|
||||
du_pins: du {
|
||||
data {
|
||||
pinmux = <RZG2L_PORT_PINMUX(11, 2, 6)>,
|
||||
<RZG2L_PORT_PINMUX(13, 1, 6)>,
|
||||
<RZG2L_PORT_PINMUX(13, 0, 6)>,
|
||||
<RZG2L_PORT_PINMUX(13, 4, 6)>,
|
||||
<RZG2L_PORT_PINMUX(13, 3, 6)>,
|
||||
<RZG2L_PORT_PINMUX(12, 1, 6)>,
|
||||
<RZG2L_PORT_PINMUX(13, 2, 6)>,
|
||||
<RZG2L_PORT_PINMUX(14, 0, 6)>,
|
||||
<RZG2L_PORT_PINMUX(14, 2, 6)>,
|
||||
<RZG2L_PORT_PINMUX(14, 1, 6)>,
|
||||
<RZG2L_PORT_PINMUX(16, 0, 6)>,
|
||||
<RZG2L_PORT_PINMUX(15, 0, 6)>,
|
||||
<RZG2L_PORT_PINMUX(16, 1, 6)>,
|
||||
<RZG2L_PORT_PINMUX(15, 1, 6)>,
|
||||
<RZG2L_PORT_PINMUX(15, 3, 6)>,
|
||||
<RZG2L_PORT_PINMUX(18, 0, 6)>,
|
||||
<RZG2L_PORT_PINMUX(15, 2, 6)>,
|
||||
<RZG2L_PORT_PINMUX(17, 0, 6)>,
|
||||
<RZG2L_PORT_PINMUX(17, 2, 6)>,
|
||||
<RZG2L_PORT_PINMUX(17, 1, 6)>,
|
||||
<RZG2L_PORT_PINMUX(18, 1, 6)>,
|
||||
<RZG2L_PORT_PINMUX(18, 2, 6)>,
|
||||
<RZG2L_PORT_PINMUX(17, 3, 6)>,
|
||||
<RZG2L_PORT_PINMUX(18, 3, 6)>;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
sync {
|
||||
pinmux = <RZG2L_PORT_PINMUX(11, 0, 6)>, /* HSYNC */
|
||||
<RZG2L_PORT_PINMUX(12, 0, 6)>; /* VSYNC */
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
de {
|
||||
pinmux = <RZG2L_PORT_PINMUX(11, 1, 6)>; /* DE */
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
clk {
|
||||
pinmux = <RZG2L_PORT_PINMUX(11, 3, 6)>; /* CLK */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1043,8 +1043,8 @@
|
|||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x11900000 0 0x40000>,
|
||||
<0x0 0x11940000 0 0x60000>;
|
||||
reg = <0x0 0x11900000 0 0x20000>,
|
||||
<0x0 0x11940000 0 0x40000>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
|
|
@ -1129,6 +1129,10 @@
|
|||
power-domains = <&cpg>;
|
||||
#reset-cells = <1>;
|
||||
status = "disabled";
|
||||
|
||||
usb0_vbus_otg: regulator-vbus {
|
||||
regulator-name = "vbus";
|
||||
};
|
||||
};
|
||||
|
||||
ohci0: usb@11c50000 {
|
||||
|
|
|
|||
|
|
@ -47,6 +47,9 @@
|
|||
#error "Cannot set as both PMOD_MTU3 and SW_RSPI_CAN are mutually exclusive"
|
||||
#endif
|
||||
|
||||
/* Please set SW_I2S0_I2S1. Default value is 0 */
|
||||
#define SW_I2S0_I2S1 0
|
||||
|
||||
#include "r9a07g044c2.dtsi"
|
||||
#include "rzg2lc-smarc-som.dtsi"
|
||||
#include "rzg2lc-smarc.dtsi"
|
||||
|
|
|
|||
|
|
@ -1051,8 +1051,8 @@
|
|||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x11900000 0 0x40000>,
|
||||
<0x0 0x11940000 0 0x60000>;
|
||||
reg = <0x0 0x11900000 0 0x20000>,
|
||||
<0x0 0x11940000 0 0x40000>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
|
|
@ -1137,6 +1137,10 @@
|
|||
power-domains = <&cpg>;
|
||||
#reset-cells = <1>;
|
||||
status = "disabled";
|
||||
|
||||
usb0_vbus_otg: regulator-vbus {
|
||||
regulator-name = "vbus";
|
||||
};
|
||||
};
|
||||
|
||||
ohci0: usb@11c50000 {
|
||||
|
|
|
|||
|
|
@ -72,6 +72,94 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@10090000 {
|
||||
compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
|
||||
reg = <0 0x10090000 0 0x400>;
|
||||
interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD R9A08G045_I2C0_PCLK>;
|
||||
clock-frequency = <100000>;
|
||||
resets = <&cpg R9A08G045_I2C0_MRST>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@10090400 {
|
||||
compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
|
||||
reg = <0 0x10090400 0 0x400>;
|
||||
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 272 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD R9A08G045_I2C1_PCLK>;
|
||||
clock-frequency = <100000>;
|
||||
resets = <&cpg R9A08G045_I2C1_MRST>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@10090800 {
|
||||
compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
|
||||
reg = <0 0x10090800 0 0x400>;
|
||||
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 279 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 280 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD R9A08G045_I2C2_PCLK>;
|
||||
clock-frequency = <100000>;
|
||||
resets = <&cpg R9A08G045_I2C2_MRST>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@10090c00 {
|
||||
compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
|
||||
reg = <0 0x10090c00 0 0x400>;
|
||||
interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 287 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD R9A08G045_I2C3_PCLK>;
|
||||
clock-frequency = <100000>;
|
||||
resets = <&cpg R9A08G045_I2C3_MRST>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpg: clock-controller@11010000 {
|
||||
compatible = "renesas,r9a08g045-cpg";
|
||||
reg = <0 0x11010000 0 0x10000>;
|
||||
|
|
@ -307,8 +395,8 @@
|
|||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x12400000 0 0x40000>,
|
||||
<0x0 0x12440000 0 0x60000>;
|
||||
reg = <0x0 0x12400000 0 0x20000>,
|
||||
<0x0 0x12440000 0 0x40000>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
|
|
|
|||
513
arch/arm64/boot/dts/renesas/r9a09g057.dtsi
Normal file
513
arch/arm64/boot/dts/renesas/r9a09g057.dtsi
Normal file
|
|
@ -0,0 +1,513 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Device Tree Source for the RZ/V2H(P) SoC
|
||||
*
|
||||
* Copyright (C) 2024 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r9a09g057";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
audio_extal_clk: audio-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0>;
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&L3_CA55>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu1: cpu@100 {
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x100>;
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&L3_CA55>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu2: cpu@200 {
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x200>;
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&L3_CA55>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu3: cpu@300 {
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x300>;
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&L3_CA55>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
L3_CA55: cache-controller-0 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-size = <0x100000>;
|
||||
cache-level = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
qextal_clk: qextal-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
rtxin_clk: rtxin-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
pinctrl: pinctrl@10410000 {
|
||||
compatible = "renesas,r9a09g057-pinctrl";
|
||||
reg = <0 0x10410000 0 0x10000>;
|
||||
clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pinctrl 0 0 96>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
power-domains = <&cpg>;
|
||||
resets = <&cpg 0xa5>, <&cpg 0xa6>;
|
||||
};
|
||||
|
||||
cpg: clock-controller@10420000 {
|
||||
compatible = "renesas,r9a09g057-cpg";
|
||||
reg = <0 0x10420000 0 0x10000>;
|
||||
clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
|
||||
clock-names = "audio_extal", "rtxin", "qextal";
|
||||
#clock-cells = <2>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
sys: system-controller@10430000 {
|
||||
compatible = "renesas,r9a09g057-sys";
|
||||
reg = <0 0x10430000 0 0x10000>;
|
||||
clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>;
|
||||
resets = <&cpg 0x30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ostm0: timer@11800000 {
|
||||
compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
|
||||
reg = <0x0 0x11800000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD 0x43>;
|
||||
resets = <&cpg 0x6d>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ostm1: timer@11801000 {
|
||||
compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
|
||||
reg = <0x0 0x11801000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD 0x44>;
|
||||
resets = <&cpg 0x6e>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ostm2: timer@14000000 {
|
||||
compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
|
||||
reg = <0x0 0x14000000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD 0x45>;
|
||||
resets = <&cpg 0x6f>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ostm3: timer@14001000 {
|
||||
compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
|
||||
reg = <0x0 0x14001000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD 0x46>;
|
||||
resets = <&cpg 0x70>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ostm4: timer@12c00000 {
|
||||
compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
|
||||
reg = <0x0 0x12c00000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD 0x47>;
|
||||
resets = <&cpg 0x71>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ostm5: timer@12c01000 {
|
||||
compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
|
||||
reg = <0x0 0x12c01000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD 0x48>;
|
||||
resets = <&cpg 0x72>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ostm6: timer@12c02000 {
|
||||
compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
|
||||
reg = <0x0 0x12c02000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD 0x49>;
|
||||
resets = <&cpg 0x73>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ostm7: timer@12c03000 {
|
||||
compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
|
||||
reg = <0x0 0x12c03000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD 0x4a>;
|
||||
resets = <&cpg 0x74>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt0: watchdog@11c00400 {
|
||||
compatible = "renesas,r9a09g057-wdt";
|
||||
reg = <0 0x11c00400 0 0x400>;
|
||||
clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
|
||||
clock-names = "pclk", "oscclk";
|
||||
resets = <&cpg 0x75>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt1: watchdog@14400000 {
|
||||
compatible = "renesas,r9a09g057-wdt";
|
||||
reg = <0 0x14400000 0 0x400>;
|
||||
clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>;
|
||||
clock-names = "pclk", "oscclk";
|
||||
resets = <&cpg 0x76>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt2: watchdog@13000000 {
|
||||
compatible = "renesas,r9a09g057-wdt";
|
||||
reg = <0 0x13000000 0 0x400>;
|
||||
clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;
|
||||
clock-names = "pclk", "oscclk";
|
||||
resets = <&cpg 0x77>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt3: watchdog@13000400 {
|
||||
compatible = "renesas,r9a09g057-wdt";
|
||||
reg = <0 0x13000400 0 0x400>;
|
||||
clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;
|
||||
clock-names = "pclk", "oscclk";
|
||||
resets = <&cpg 0x78>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif: serial@11c01400 {
|
||||
compatible = "renesas,scif-r9a09g057";
|
||||
reg = <0 0x11c01400 0 0x400>;
|
||||
interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 536 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 537 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "eri", "rxi", "txi", "bri", "dri",
|
||||
"tei", "tei-dri", "rxi-edge", "txi-edge";
|
||||
clocks = <&cpg CPG_MOD 0x8f>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg>;
|
||||
resets = <&cpg 0x95>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@14400400 {
|
||||
compatible = "renesas,riic-r9a09g057";
|
||||
reg = <0 0x14400400 0 0x400>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 507 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 506 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD 0x94>;
|
||||
resets = <&cpg 0x98>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@14400800 {
|
||||
compatible = "renesas,riic-r9a09g057";
|
||||
reg = <0 0x14400800 0 0x400>;
|
||||
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 509 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 508 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD 0x95>;
|
||||
resets = <&cpg 0x99>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@14400c00 {
|
||||
compatible = "renesas,riic-r9a09g057";
|
||||
reg = <0 0x14400c00 0 0x400>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 511 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 510 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD 0x96>;
|
||||
resets = <&cpg 0x9a>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@14401000 {
|
||||
compatible = "renesas,riic-r9a09g057";
|
||||
reg = <0 0x14401000 0 0x400>;
|
||||
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 513 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 512 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD 0x97>;
|
||||
resets = <&cpg 0x9b>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@14401400 {
|
||||
compatible = "renesas,riic-r9a09g057";
|
||||
reg = <0 0x14401400 0 0x400>;
|
||||
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 515 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 514 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD 0x98>;
|
||||
resets = <&cpg 0x9c>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@14401800 {
|
||||
compatible = "renesas,riic-r9a09g057";
|
||||
reg = <0 0x14401800 0 0x400>;
|
||||
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 517 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 516 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD 0x99>;
|
||||
resets = <&cpg 0x9d>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c@14401c00 {
|
||||
compatible = "renesas,riic-r9a09g057";
|
||||
reg = <0 0x14401c00 0 0x400>;
|
||||
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 519 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 518 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD 0x9a>;
|
||||
resets = <&cpg 0x9e>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c7: i2c@14402000 {
|
||||
compatible = "renesas,riic-r9a09g057";
|
||||
reg = <0 0x14402000 0 0x400>;
|
||||
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 521 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 520 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD 0x9b>;
|
||||
resets = <&cpg 0x9f>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c8: i2c@11c01000 {
|
||||
compatible = "renesas,riic-r9a09g057";
|
||||
reg = <0 0x11c01000 0 0x400>;
|
||||
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 523 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 522 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
||||
"naki", "ali", "tmoi";
|
||||
clocks = <&cpg CPG_MOD 0x93>;
|
||||
resets = <&cpg 0xa0>;
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@14900000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x0 0x14900000 0 0x20000>,
|
||||
<0x0 0x14940000 0 0x80000>;
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
sdhi0: mmc@15c00000 {
|
||||
compatible = "renesas,sdhi-r9a09g057";
|
||||
reg = <0x0 0x15c00000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>,
|
||||
<&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>;
|
||||
clock-names = "core", "clkh", "cd", "aclk";
|
||||
resets = <&cpg 0xa7>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi1: mmc@15c10000 {
|
||||
compatible = "renesas,sdhi-r9a09g057";
|
||||
reg = <0x0 0x15c10000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>,
|
||||
<&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>;
|
||||
clock-names = "core", "clkh", "cd", "aclk";
|
||||
resets = <&cpg 0xa8>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi2: mmc@15c20000 {
|
||||
compatible = "renesas,sdhi-r9a09g057";
|
||||
reg = <0x0 0x15c20000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>,
|
||||
<&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>;
|
||||
clock-names = "core", "clkh", "cd", "aclk";
|
||||
resets = <&cpg 0xa9>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
|
||||
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
|
||||
};
|
||||
};
|
||||
256
arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
Normal file
256
arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
Normal file
|
|
@ -0,0 +1,256 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Device Tree Source for the RZ/V2H EVK board
|
||||
*
|
||||
* Copyright (C) 2024 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "r9a09g057.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Renesas RZ/V2H EVK Board based on r9a09g057h44";
|
||||
compatible = "renesas,rzv2h-evk", "renesas,r9a09g057h44", "renesas,r9a09g057";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c6 = &i2c6;
|
||||
i2c7 = &i2c7;
|
||||
i2c8 = &i2c8;
|
||||
mmc1 = &sdhi1;
|
||||
serial0 = &scif;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x1 0xF8000000>;
|
||||
};
|
||||
|
||||
memory@240000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x2 0x40000000 0x2 0x00000000>;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator1 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vqmmc_sdhi1: regulator-vccq-sdhi1 {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "SDHI1 VccQ";
|
||||
gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios-states = <0>;
|
||||
states = <3300000 0>, <1800000 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&audio_extal_clk {
|
||||
clock-frequency = <22579200>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-0 = <&i2c3_pins>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
pinctrl-0 = <&i2c6_pins>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
pinctrl-0 = <&i2c7_pins>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c8 {
|
||||
pinctrl-0 = <&i2c8_pins>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
i2c0_pins: i2c0 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */
|
||||
<RZG2L_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(3, 2, 1)>, /* I2C1_SDA */
|
||||
<RZG2L_PORT_PINMUX(3, 3, 1)>; /* I2C1_SCL */
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(2, 0, 4)>, /* I2C2_SDA */
|
||||
<RZG2L_PORT_PINMUX(2, 1, 4)>; /* I2C2_SCL */
|
||||
};
|
||||
|
||||
i2c3_pins: i2c3 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(3, 6, 1)>, /* I2C3_SDA */
|
||||
<RZG2L_PORT_PINMUX(3, 7, 1)>; /* I2C3_SCL */
|
||||
};
|
||||
|
||||
i2c6_pins: i2c6 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(4, 4, 1)>, /* I2C6_SDA */
|
||||
<RZG2L_PORT_PINMUX(4, 5, 1)>; /* I2C6_SCL */
|
||||
};
|
||||
|
||||
i2c7_pins: i2c7 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(4, 6, 1)>, /* I2C7_SDA */
|
||||
<RZG2L_PORT_PINMUX(4, 7, 1)>; /* I2C7_SCL */
|
||||
};
|
||||
|
||||
i2c8_pins: i2c8 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(0, 6, 1)>, /* I2C8_SDA */
|
||||
<RZG2L_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */
|
||||
};
|
||||
|
||||
scif_pins: scif {
|
||||
pins = "SCIF_TXD", "SCIF_RXD";
|
||||
renesas,output-impedance = <1>;
|
||||
};
|
||||
|
||||
sd1-pwr-en-hog {
|
||||
gpio-hog;
|
||||
gpios = <RZG2L_GPIO(10, 3) GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "sd1_pwr_en";
|
||||
};
|
||||
|
||||
sdhi1_pins: sd1 {
|
||||
sd1_dat_cmd {
|
||||
pins = "SD1DAT0", "SD1DAT1", "SD1DAT2", "SD1DAT3", "SD1CMD";
|
||||
input-enable;
|
||||
renesas,output-impedance = <3>;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
|
||||
sd1_clk {
|
||||
pins = "SD1CLK";
|
||||
renesas,output-impedance = <3>;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
|
||||
sd1_cd {
|
||||
pinmux = <RZG2L_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qextal_clk {
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
&rtxin_clk {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
&scif {
|
||||
pinctrl-0 = <&scif_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi1 {
|
||||
pinctrl-0 = <&sdhi1_pins>;
|
||||
pinctrl-1 = <&sdhi1_pins>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <&vqmmc_sdhi1>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -131,9 +131,6 @@
|
|||
|
||||
&phyrst {
|
||||
status = "okay";
|
||||
usb0_vbus_otg: regulator-vbus {
|
||||
regulator-name = "vbus";
|
||||
};
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
|
|
|
|||
76
arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi
Normal file
76
arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi
Normal file
|
|
@ -0,0 +1,76 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Common Device Tree for the RZ/G2UL SMARC EVK (and alike EVKs) with
|
||||
* ADV7513 transmitter connected to DU enabled.
|
||||
*
|
||||
* Copyright (C) 2024 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
&{/} {
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "d";
|
||||
|
||||
port {
|
||||
hdmi_con_out: endpoint {
|
||||
remote-endpoint = <&adv7513_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
du_out_rgb: endpoint {
|
||||
remote-endpoint = <&adv7513_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ADV7513_PARENT_I2C {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
adv7513: adv7513@39 {
|
||||
compatible = "adi,adv7513";
|
||||
reg = <0x39>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
|
||||
avdd-supply = <®_1p8v>;
|
||||
dvdd-supply = <®_1p8v>;
|
||||
pvdd-supply = <®_1p8v>;
|
||||
dvdd-3v-supply = <®_3p3v>;
|
||||
bgvdd-supply = <®_1p8v>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
adv7513_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
adv7513_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -143,6 +143,12 @@
|
|||
<RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
|
||||
};
|
||||
|
||||
ssi1_pins: ssi1 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(46, 0, 1)>, /* BCK */
|
||||
<RZG2L_PORT_PINMUX(46, 1, 1)>, /* RCK */
|
||||
<RZG2L_PORT_PINMUX(46, 2, 1)>; /* TXD */
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
|
||||
<RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
|
||||
|
|
|
|||
|
|
@ -30,6 +30,12 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
sound_card {
|
||||
compatible = "audio-graph-card";
|
||||
label = "HDMI-Audio";
|
||||
dais = <&i2s2_port>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_dai {
|
||||
|
|
@ -88,6 +94,13 @@
|
|||
remote-endpoint = <&hdmi_con_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
codec_endpoint: endpoint {
|
||||
remote-endpoint = <&i2s2_cpu_endpoint>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -170,6 +183,23 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
pinctrl-0 = <&ssi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
i2s2_port: port {
|
||||
i2s2_cpu_endpoint: endpoint {
|
||||
remote-endpoint = <&codec_endpoint>;
|
||||
dai-format = "i2s";
|
||||
|
||||
bitclock-master = <&i2s2_cpu_endpoint>;
|
||||
frame-master = <&i2s2_cpu_endpoint>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&vccq_sdhi1 {
|
||||
gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -33,6 +33,16 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
#if (SW_I2S0_I2S1)
|
||||
/delete-node/ sound;
|
||||
|
||||
sound_card {
|
||||
compatible = "audio-graph-card";
|
||||
label = "HDMI-Audio";
|
||||
dais = <&i2s2_port>;
|
||||
};
|
||||
#endif
|
||||
};
|
||||
|
||||
#if (SW_SCIF_CAN || SW_RSPI_CAN)
|
||||
|
|
@ -48,9 +58,11 @@
|
|||
};
|
||||
#endif
|
||||
|
||||
#if (!SW_I2S0_I2S1)
|
||||
&cpu_dai {
|
||||
sound-dai = <&ssi0>;
|
||||
};
|
||||
#endif
|
||||
|
||||
&dsi {
|
||||
status = "okay";
|
||||
|
|
@ -104,6 +116,15 @@
|
|||
remote-endpoint = <&hdmi_con_out>;
|
||||
};
|
||||
};
|
||||
|
||||
#if (SW_I2S0_I2S1)
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
codec_endpoint: endpoint {
|
||||
remote-endpoint = <&i2s2_cpu_endpoint>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -177,6 +198,18 @@
|
|||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
#if (SW_I2S0_I2S1)
|
||||
i2s2_port: port {
|
||||
i2s2_cpu_endpoint: endpoint {
|
||||
remote-endpoint = <&codec_endpoint>;
|
||||
dai-format = "i2s";
|
||||
|
||||
bitclock-master = <&i2s2_cpu_endpoint>;
|
||||
frame-master = <&i2s2_cpu_endpoint>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
};
|
||||
|
||||
#if (SW_RSPI_CAN)
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
|
||||
|
||||
aliases {
|
||||
i2c1 = &i2c1;
|
||||
mmc0 = &sdhi0;
|
||||
#if SW_CONFIG3 == SW_OFF
|
||||
mmc2 = &sdhi2;
|
||||
|
|
@ -150,6 +151,10 @@
|
|||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#if SW_CONFIG2 == SW_ON
|
||||
/* SD0 slot */
|
||||
&sdhi0 {
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
|
||||
/ {
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
serial0 = &scif0;
|
||||
mmc1 = &sdhi1;
|
||||
};
|
||||
|
|
@ -66,6 +67,12 @@
|
|||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
key-1-gpio-hog {
|
||||
gpio-hog;
|
||||
|
|
|
|||
|
|
@ -117,6 +117,12 @@
|
|||
};
|
||||
};
|
||||
|
||||
pcie_clk: clk-9fgv0841-pci {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <100000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
reg_1p2v: regulator-1p2v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.2V";
|
||||
|
|
@ -288,6 +294,18 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0_clkref {
|
||||
compatible = "gpio-gate-clock";
|
||||
clocks = <&pcie_clk>;
|
||||
enable-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
|
||||
/delete-property/ clock-frequency;
|
||||
};
|
||||
|
||||
&pciec0 {
|
||||
reset-gpio = <&io_expander_a 0 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
|
|||
21
include/dt-bindings/clock/renesas,r9a09g057-cpg.h
Normal file
21
include/dt-bindings/clock/renesas,r9a09g057-cpg.h
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
*
|
||||
* Copyright (C) 2024 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__
|
||||
#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* Core Clock list */
|
||||
#define R9A09G057_SYS_0_PCLK 0
|
||||
#define R9A09G057_CA55_0_CORE_CLK0 1
|
||||
#define R9A09G057_CA55_0_CORE_CLK1 2
|
||||
#define R9A09G057_CA55_0_CORE_CLK2 3
|
||||
#define R9A09G057_CA55_0_CORE_CLK3 4
|
||||
#define R9A09G057_CA55_0_PERIPHCLK 5
|
||||
#define R9A09G057_CM33_CLK0 6
|
||||
#define R9A09G057_CST_0_SWCLKTCK 7
|
||||
#define R9A09G057_IOTOP_0_SHCLK 8
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */
|
||||
Loading…
Reference in New Issue
Block a user