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iio: frequency: ad9523: Fix typo in ad9523_platform_data
Replace diff_{m1,m2} with div_{m1,m2} since they are dividers and not a differential settings. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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@ -872,22 +872,22 @@ static int ad9523_setup(struct iio_dev *indio_dev)
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return ret;
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return ret;
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ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_DIVIDER,
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ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_DIVIDER,
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AD9523_PLL2_VCO_DIV_M1(pdata->pll2_vco_diff_m1) |
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AD9523_PLL2_VCO_DIV_M1(pdata->pll2_vco_div_m1) |
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AD9523_PLL2_VCO_DIV_M2(pdata->pll2_vco_diff_m2) |
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AD9523_PLL2_VCO_DIV_M2(pdata->pll2_vco_div_m2) |
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AD_IFE(pll2_vco_diff_m1, 0,
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AD_IFE(pll2_vco_div_m1, 0,
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AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN) |
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AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN) |
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AD_IFE(pll2_vco_diff_m2, 0,
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AD_IFE(pll2_vco_div_m2, 0,
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AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN));
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AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN));
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if (ret < 0)
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if (ret < 0)
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return ret;
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return ret;
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if (pdata->pll2_vco_diff_m1)
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if (pdata->pll2_vco_div_m1)
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st->vco_out_freq[AD9523_VCO1] =
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st->vco_out_freq[AD9523_VCO1] =
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st->vco_freq / pdata->pll2_vco_diff_m1;
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st->vco_freq / pdata->pll2_vco_div_m1;
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if (pdata->pll2_vco_diff_m2)
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if (pdata->pll2_vco_div_m2)
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st->vco_out_freq[AD9523_VCO2] =
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st->vco_out_freq[AD9523_VCO2] =
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st->vco_freq / pdata->pll2_vco_diff_m2;
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st->vco_freq / pdata->pll2_vco_div_m2;
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st->vco_out_freq[AD9523_VCXO] = pdata->vcxo_freq;
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st->vco_out_freq[AD9523_VCXO] = pdata->vcxo_freq;
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@ -129,8 +129,8 @@ enum cpole1_capacitor {
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* @pll2_ndiv_b_cnt: PLL2 Feedback N-divider, B Counter, range 0..63.
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* @pll2_ndiv_b_cnt: PLL2 Feedback N-divider, B Counter, range 0..63.
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* @pll2_freq_doubler_en: PLL2 frequency doubler enable.
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* @pll2_freq_doubler_en: PLL2 frequency doubler enable.
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* @pll2_r2_div: PLL2 R2 divider, range 0..31.
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* @pll2_r2_div: PLL2 R2 divider, range 0..31.
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* @pll2_vco_diff_m1: VCO1 divider, range 3..5.
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* @pll2_vco_div_m1: VCO1 divider, range 3..5.
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* @pll2_vco_diff_m2: VCO2 divider, range 3..5.
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* @pll2_vco_div_m2: VCO2 divider, range 3..5.
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* @rpole2: PLL2 loop filter Rpole resistor value.
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* @rpole2: PLL2 loop filter Rpole resistor value.
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* @rzero: PLL2 loop filter Rzero resistor value.
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* @rzero: PLL2 loop filter Rzero resistor value.
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* @cpole1: PLL2 loop filter Cpole capacitor value.
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* @cpole1: PLL2 loop filter Cpole capacitor value.
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@ -176,8 +176,8 @@ struct ad9523_platform_data {
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unsigned char pll2_ndiv_b_cnt;
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unsigned char pll2_ndiv_b_cnt;
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bool pll2_freq_doubler_en;
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bool pll2_freq_doubler_en;
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unsigned char pll2_r2_div;
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unsigned char pll2_r2_div;
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unsigned char pll2_vco_diff_m1; /* 3..5 */
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unsigned char pll2_vco_div_m1; /* 3..5 */
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unsigned char pll2_vco_diff_m2; /* 3..5 */
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unsigned char pll2_vco_div_m2; /* 3..5 */
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/* Loop Filter PLL2 */
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/* Loop Filter PLL2 */
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enum rpole2_resistor rpole2;
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enum rpole2_resistor rpole2;
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