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drm/stm: dsi: compute the transition time from LP to HS and back

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The driver uses a conservative set of hardcoded values for the
maximum time delay of the transitions between LP and HS, either
for data and clock lanes.

By using the info in STM32MP157 datasheet, valid also for other ST
devices, compute the actual delay from the lane's bps.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Philippe Cornu <philippe.cornu@foss.st.com>
Acked-by: Philippe Cornu <philippe.cornu@foss.st.com>
Signed-off-by: Philippe Cornu <philippe.cornu@foss.st.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210713144941.3599-1-antonio.borneo@foss.st.com
This commit is contained in:
Antonio Borneo 2021-07-13 16:49:41 +02:00 committed by Philippe Cornu
parent 648ce7fd18
commit 5cc4e71f01
1 changed files with 13 additions and 4 deletions
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17
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
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@ -309,14 +309,23 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
return 0;
}
#define DSI_PHY_DELAY(fp, vp, mbps) DIV_ROUND_UP((fp) * (mbps) + 1000 * (vp), 8000)
static int
dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
struct dw_mipi_dsi_dphy_timing *timing)
{
timing->clk_hs2lp = 0x40;
timing->clk_lp2hs = 0x40;
timing->data_hs2lp = 0x40;
timing->data_lp2hs = 0x40;
/*
* From STM32MP157 datasheet, valid for STM32F469, STM32F7x9, STM32H747
* phy_clkhs2lp_time = (272+136*UI)/(8*UI)
* phy_clklp2hs_time = (512+40*UI)/(8*UI)
* phy_hs2lp_time = (192+64*UI)/(8*UI)
* phy_lp2hs_time = (256+32*UI)/(8*UI)
*/
timing->clk_hs2lp = DSI_PHY_DELAY(272, 136, lane_mbps);
timing->clk_lp2hs = DSI_PHY_DELAY(512, 40, lane_mbps);
timing->data_hs2lp = DSI_PHY_DELAY(192, 64, lane_mbps);
timing->data_lp2hs = DSI_PHY_DELAY(256, 32, lane_mbps);
return 0;
}