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KVM: x86: Move CPUID.(EAX=0x12,ECX=1) mangling to __kvm_update_cpuid_runtime()
Full equality check of CPUID data on update (kvm_cpuid_check_equal()) may
fail for SGX enabled CPUs as CPUID.(EAX=0x12,ECX=1) is currently being
mangled in kvm_vcpu_after_set_cpuid(). Move it to
__kvm_update_cpuid_runtime() and split off cpuid_get_supported_xcr0()
helper as 'vcpu->arch.guest_supported_xcr0' update needs (logically)
to stay in kvm_vcpu_after_set_cpuid().
Cc: stable@vger.kernel.org
Fixes: feb627e8d6
("KVM: x86: Forbid KVM_SET_CPUID{,2} after KVM_RUN")
Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Message-Id: <20220124103606.2630588-2-vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
parent
1625566ec8
commit
5c89be1dd5
@ -196,10 +196,26 @@ void kvm_update_pv_runtime(struct kvm_vcpu *vcpu)
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vcpu->arch.pv_cpuid.features = best->eax;
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}
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/*
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* Calculate guest's supported XCR0 taking into account guest CPUID data and
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* supported_xcr0 (comprised of host configuration and KVM_SUPPORTED_XCR0).
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*/
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static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent)
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{
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struct kvm_cpuid_entry2 *best;
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best = cpuid_entry2_find(entries, nent, 0xd, 0);
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if (!best)
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return 0;
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return (best->eax | ((u64)best->edx << 32)) & supported_xcr0;
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}
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static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries,
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int nent)
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{
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struct kvm_cpuid_entry2 *best;
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u64 guest_supported_xcr0 = cpuid_get_supported_xcr0(entries, nent);
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best = cpuid_entry2_find(entries, nent, 1, 0);
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if (best) {
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@ -238,6 +254,21 @@ static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_e
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vcpu->arch.ia32_misc_enable_msr &
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MSR_IA32_MISC_ENABLE_MWAIT);
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}
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/*
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* Bits 127:0 of the allowed SECS.ATTRIBUTES (CPUID.0x12.0x1) enumerate
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* the supported XSAVE Feature Request Mask (XFRM), i.e. the enclave's
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* requested XCR0 value. The enclave's XFRM must be a subset of XCRO
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* at the time of EENTER, thus adjust the allowed XFRM by the guest's
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* supported XCR0. Similar to XCR0 handling, FP and SSE are forced to
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* '1' even on CPUs that don't support XSAVE.
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*/
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best = cpuid_entry2_find(entries, nent, 0x12, 0x1);
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if (best) {
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best->ecx &= guest_supported_xcr0 & 0xffffffff;
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best->edx &= guest_supported_xcr0 >> 32;
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best->ecx |= XFEATURE_MASK_FPSSE;
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}
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}
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void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu)
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@ -261,27 +292,8 @@ static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
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kvm_apic_set_version(vcpu);
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}
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best = kvm_find_cpuid_entry(vcpu, 0xD, 0);
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if (!best)
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vcpu->arch.guest_supported_xcr0 = 0;
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else
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vcpu->arch.guest_supported_xcr0 =
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(best->eax | ((u64)best->edx << 32)) & supported_xcr0;
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/*
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* Bits 127:0 of the allowed SECS.ATTRIBUTES (CPUID.0x12.0x1) enumerate
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* the supported XSAVE Feature Request Mask (XFRM), i.e. the enclave's
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* requested XCR0 value. The enclave's XFRM must be a subset of XCRO
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* at the time of EENTER, thus adjust the allowed XFRM by the guest's
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* supported XCR0. Similar to XCR0 handling, FP and SSE are forced to
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* '1' even on CPUs that don't support XSAVE.
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*/
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best = kvm_find_cpuid_entry(vcpu, 0x12, 0x1);
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if (best) {
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best->ecx &= vcpu->arch.guest_supported_xcr0 & 0xffffffff;
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best->edx &= vcpu->arch.guest_supported_xcr0 >> 32;
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best->ecx |= XFEATURE_MASK_FPSSE;
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}
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vcpu->arch.guest_supported_xcr0 =
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cpuid_get_supported_xcr0(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent);
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kvm_update_pv_runtime(vcpu);
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