Pin control fixes for the v4.9 cycle:

- Fix a host of runtime problems with the Intel
   Cherryview driver: suspend/resume needs to be
   marshalled properly, and strange effects from BIOS
   interaction during suspend/resume need to be
   dealt with.
 
 - A single bit was being set wrong in the Aspeed
   driver.
 
 - Fix an iProc probe ordering fallout resulting from
   v4.9 refactorings for bus population.
 
 - Do not specify a default trigger in the ST Micro
   cascaded GPIO IRQ controller: the kernel will moan.
 
 - Make IRQs optional altogether on the STM32 driver,
   it turns out not all systems have them or want them.
 
 - Fix a re-probe bug in the i.MX driver, it will
   eventually crash if probed repeatedly, not good.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABAgAGBQJYJDVGAAoJEEEQszewGV1zfjsQAMC2imdzCSsS2NYq9+Ua2MKk
 oWtPHLY5hnCOm6lrcj7kI1OxiE14E6eQ/ufg82Zl8Yg6v9P1RfrtSJI23bsXZUou
 Q+Fw4J3RIjnakpj9cLt3iSWLkg5RvjQQWDiRgoFyVSKntR+0r4UE7P5VUPr7Q4Oe
 fmDZWe7caBtjan7cFNuKg6UpmjOhydLOSYRrchhoJfwXPFDJJueQkgn7XWifIlG2
 pTJIg8YmRruzj2zoW9zKgGEeeHi20JIhSmZLKwHFxYdSmOBMuCwDypM3uTXcDBuy
 2RyB9UKg7uAgaaMseX3zcjSjZMlsXNCVBCVHJXbaVmc3ZyTj8uYG/bqzdpu0mVRZ
 Iyxm3ao5g4lbm4ahBoWOsynXVJNUP71Fu9UKcW29Z6GuaNdEFIngRH6k/YB2vcBi
 IhM4Qd3thNQ3eYOkX0jSNv92wIANqTgalsr8t+Qb8g4Z2TVokg1fb0hsIoj78dCH
 1ZSo/0rSW20YsUcK1/yVhZArkbVb9ABSPWbj1OW4BbsZBhqetxtZ6ZNDjSjwbJDg
 G6Rh8I2pXZ4DL2rXIQ84rXdzMgYOx6fBjIOiRcehP3GQNBsDpBiU1Xb4Rw27c2vX
 sW19tRiPZDJDFuUIs52wvUFUHTMdFb1nwtYFYxRr7Siob4/HIGUWJ3UN+/2gqy94
 woCRmI/jTzGHQrWRGm5I
 =ENR8
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v4.9-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
 "All is about drivers, no core business going on.

   - Fix a host of runtime problems with the Intel Cherryview driver:
     suspend/resume needs to be marshalled properly, and strange effects
     from BIOS interaction during suspend/resume need to be dealt with.

   - A single bit was being set wrong in the Aspeed driver.

   - Fix an iProc probe ordering fallout resulting from v4.9
     refactorings for bus population.

   - Do not specify a default trigger in the ST Micro cascaded GPIO IRQ
     controller: the kernel will moan.

   - Make IRQs optional altogether on the STM32 driver, it turns out not
     all systems have them or want them.

   - Fix a re-probe bug in the i.MX driver, it will eventually crash if
     probed repeatedly, not good"

* tag 'pinctrl-v4.9-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl-aspeed-g5: Never set SCU90[6]
  pinctrl: cherryview: Prevent possible interrupt storm on resume
  pinctrl: cherryview: Serialize register access in suspend/resume
  pinctrl: imx: reset group index on probe
  pinctrl: stm32: move gpio irqs binding to optional
  pinctrl: stm32: remove dependency with interrupt controller
  pinctrl: st: don't specify default interrupt trigger
  pinctrl: iproc: Fix iProc and NSP GPIO support
This commit is contained in:
Linus Torvalds 2016-11-11 16:21:20 -08:00
commit 5c03b53cb7
8 changed files with 29 additions and 15 deletions

View File

@ -14,11 +14,6 @@ Required properies:
- #size-cells : The value of this property must be 1
- ranges : defines mapping between pin controller node (parent) to
gpio-bank node (children).
- interrupt-parent: phandle of the interrupt parent to which the external
GPIO interrupts are forwarded to.
- st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
which includes IRQ mux selection register, and the offset of the IRQ mux
selection register.
- pins-are-numbered: Specify the subnodes are using numbered pinmux to
specify pins.
@ -37,6 +32,11 @@ Required properties:
Optional properties:
- reset: : Reference to the reset controller
- interrupt-parent: phandle of the interrupt parent to which the external
GPIO interrupts are forwarded to.
- st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
which includes IRQ mux selection register, and the offset of the IRQ mux
selection register.
Example:
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>

View File

@ -26,7 +26,7 @@
#define ASPEED_G5_NR_PINS 228
#define COND1 SIG_DESC_BIT(SCU90, 6, 0)
#define COND1 { SCU90, BIT(6), 0, 0 }
#define COND2 { SCU94, GENMASK(1, 0), 0, 0 }
#define B14 0

View File

@ -844,6 +844,6 @@ static struct platform_driver iproc_gpio_driver = {
static int __init iproc_gpio_init(void)
{
return platform_driver_probe(&iproc_gpio_driver, iproc_gpio_probe);
return platform_driver_register(&iproc_gpio_driver);
}
arch_initcall_sync(iproc_gpio_init);

View File

@ -741,6 +741,6 @@ static struct platform_driver nsp_gpio_driver = {
static int __init nsp_gpio_init(void)
{
return platform_driver_probe(&nsp_gpio_driver, nsp_gpio_probe);
return platform_driver_register(&nsp_gpio_driver);
}
arch_initcall_sync(nsp_gpio_init);

View File

@ -687,6 +687,7 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev,
if (!info->functions)
return -ENOMEM;
info->group_index = 0;
if (flat_funcs) {
info->ngroups = of_get_child_count(np);
} else {

View File

@ -1652,12 +1652,15 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
}
#ifdef CONFIG_PM_SLEEP
static int chv_pinctrl_suspend(struct device *dev)
static int chv_pinctrl_suspend_noirq(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
unsigned long flags;
int i;
raw_spin_lock_irqsave(&chv_lock, flags);
pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK);
for (i = 0; i < pctrl->community->npins; i++) {
@ -1678,15 +1681,20 @@ static int chv_pinctrl_suspend(struct device *dev)
ctx->padctrl1 = readl(reg);
}
raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
static int chv_pinctrl_resume(struct device *dev)
static int chv_pinctrl_resume_noirq(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
unsigned long flags;
int i;
raw_spin_lock_irqsave(&chv_lock, flags);
/*
* Mask all interrupts before restoring per-pin configuration
* registers because we don't know in which state BIOS left them
@ -1731,12 +1739,15 @@ static int chv_pinctrl_resume(struct device *dev)
chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK);
raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
#endif
static const struct dev_pm_ops chv_pinctrl_pm_ops = {
SET_LATE_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend, chv_pinctrl_resume)
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq,
chv_pinctrl_resume_noirq)
};
static const struct acpi_device_id chv_pinctrl_acpi_match[] = {

View File

@ -1512,7 +1512,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info,
if (info->irqmux_base || gpio_irq > 0) {
err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip,
0, handle_simple_irq,
IRQ_TYPE_LEVEL_LOW);
IRQ_TYPE_NONE);
if (err) {
gpiochip_remove(&bank->gpio_chip);
dev_info(dev, "could not add irqchip\n");

View File

@ -1092,9 +1092,11 @@ int stm32_pctl_probe(struct platform_device *pdev)
return -EINVAL;
}
ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
if (ret)
return ret;
if (of_find_property(np, "interrupt-parent", NULL)) {
ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
if (ret)
return ret;
}
for_each_child_of_node(np, child)
if (of_property_read_bool(child, "gpio-controller"))