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parisc: Restore possibility to execute 64-bit applications
Executing 64-bit applications was broken. This patch restores this support and cleans up some code paths. Signed-off-by: Helge Deller <deller@gmx.de>
This commit is contained in:
Helge Deller
parent
c8921d72e3
commit
5b00ca0b80
@ -235,6 +235,7 @@ typedef unsigned long elf_greg_t;
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#define SET_PERSONALITY(ex) \
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({ \
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set_personality((current->personality & ~PER_MASK) | PER_LINUX); \
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clear_thread_flag(TIF_32BIT); \
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current->thread.map_base = DEFAULT_MAP_BASE; \
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current->thread.task_size = DEFAULT_TASK_SIZE; \
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})
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@ -243,9 +244,11 @@ typedef unsigned long elf_greg_t;
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#define COMPAT_SET_PERSONALITY(ex) \
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({ \
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set_thread_flag(TIF_32BIT); \
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current->thread.map_base = DEFAULT_MAP_BASE32; \
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current->thread.task_size = DEFAULT_TASK_SIZE32; \
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if ((ex).e_ident[EI_CLASS] == ELFCLASS32) { \
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set_thread_flag(TIF_32BIT); \
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current->thread.map_base = DEFAULT_MAP_BASE32; \
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current->thread.task_size = DEFAULT_TASK_SIZE32; \
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} else clear_thread_flag(TIF_32BIT); \
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})
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/*
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@ -256,11 +256,7 @@ on downward growing arches, it looks like this:
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* it in here from the current->personality
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*/
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#ifdef CONFIG_64BIT
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#define USER_WIDE_MODE (!test_thread_flag(TIF_32BIT))
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#else
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#define USER_WIDE_MODE 0
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#endif
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#define USER_WIDE_MODE (!is_32bit_task())
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#define start_thread(regs, new_pc, new_sp) do { \
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elf_addr_t *sp = (elf_addr_t *)new_sp; \
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@ -2,7 +2,9 @@
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#ifndef __ASM_TRAPS_H
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#define __ASM_TRAPS_H
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#ifdef __KERNEL__
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#define PARISC_ITLB_TRAP 6 /* defined by architecture. Do not change. */
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#if !defined(__ASSEMBLY__)
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struct pt_regs;
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/* traps.c */
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@ -36,6 +36,7 @@
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#include <asm/signal.h>
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#include <asm/unistd.h>
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#include <asm/ldcw.h>
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#include <asm/traps.h>
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#include <asm/thread_info.h>
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#include <linux/linkage.h>
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@ -692,7 +693,7 @@ ENTRY(fault_vector_20)
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def 3
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extint 4
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def 5
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itlb_20 6
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itlb_20 PARISC_ITLB_TRAP
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def 7
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def 8
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def 9
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@ -735,7 +736,7 @@ ENTRY(fault_vector_11)
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def 3
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extint 4
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def 5
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itlb_11 6
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itlb_11 PARISC_ITLB_TRAP
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def 7
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def 8
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def 9
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@ -1068,21 +1069,12 @@ ENTRY_CFI(intr_save) /* for os_hpmc */
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save_specials %r29
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/* If this trap is a itlb miss, skip saving/adjusting isr/ior */
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/*
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* FIXME: 1) Use a #define for the hardwired "6" below (and in
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* traps.c.
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* 2) Once we start executing code above 4 Gb, we need
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* to adjust iasq/iaoq here in the same way we
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* adjust isr/ior below.
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*/
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cmpib,COND(=),n 6,%r26,skip_save_ior
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cmpib,COND(=),n PARISC_ITLB_TRAP,%r26,skip_save_ior
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mfctl %cr20, %r16 /* isr */
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mfctl %isr, %r16
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nop /* serialize mfctl on PA 2.0 to avoid 4 cycle penalty */
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mfctl %cr21, %r17 /* ior */
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mfctl %ior, %r17
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#ifdef CONFIG_64BIT
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@ -1094,22 +1086,34 @@ ENTRY_CFI(intr_save) /* for os_hpmc */
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extrd,u,*<> %r8,PSW_W_BIT,1,%r0
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depdi 0,1,2,%r17
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/*
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* FIXME: This code has hardwired assumptions about the split
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* between space bits and offset bits. This will change
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* when we allow alternate page sizes.
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*/
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/* adjust isr/ior. */
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extrd,u %r16,63,SPACEID_SHIFT,%r1 /* get high bits from isr for ior */
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depd %r1,31,SPACEID_SHIFT,%r17 /* deposit them into ior */
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depdi 0,63,SPACEID_SHIFT,%r16 /* clear them from isr */
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/* adjust isr/ior: get high bits from isr and deposit in ior */
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space_adjust %r16,%r17,%r1
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#endif
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STREG %r16, PT_ISR(%r29)
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STREG %r17, PT_IOR(%r29)
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#if 0 && defined(CONFIG_64BIT)
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/* Revisit when we have 64-bit code above 4Gb */
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b,n intr_save2
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skip_save_ior:
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/* We have a itlb miss, and when executing code above 4 Gb on ILP64, we
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* need to adjust iasq/iaoq here in the same way we adjusted isr/ior
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* above.
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*/
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extrd,u,* %r8,PSW_W_BIT,1,%r1
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cmpib,COND(=),n 1,%r1,intr_save2
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LDREG PT_IASQ0(%r29), %r16
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LDREG PT_IAOQ0(%r29), %r17
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/* adjust iasq/iaoq */
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space_adjust %r16,%r17,%r1
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STREG %r16, PT_IASQ0(%r29)
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STREG %r17, PT_IAOQ0(%r29)
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#else
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skip_save_ior:
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#endif
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intr_save2:
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virt_map
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save_general %r29
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@ -156,11 +156,6 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
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int do_color_align, last_mmap;
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struct vm_unmapped_area_info info;
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#ifdef CONFIG_64BIT
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/* This should only ever run for 32-bit processes. */
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BUG_ON(!test_thread_flag(TIF_32BIT));
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#endif
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/* requested length too big for entire address space */
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if (len > TASK_SIZE)
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return -ENOMEM;
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@ -557,7 +557,7 @@ void notrace handle_interruption(int code, struct pt_regs *regs)
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cpu_lpmc(5, regs);
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return;
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case 6:
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case PARISC_ITLB_TRAP:
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/* Instruction TLB miss fault/Instruction page fault */
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fault_address = regs->iaoq[0];
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fault_space = regs->iasq[0];
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