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ARM: mpu: add MPU probe and initialisation functions in C
This patch adds new functions for probing and initialising the ARMv7 PMSA-compliant MPU. These use the pre-defined and reserved MPU_PROBE_REGION for establishing properties of the MPU, which is necessary because certain probe operations require modifying region properties and reading back the results. This patch also introduces a minimal sanity_check_meminfo_mpu function, that ensures that the memory set-up passed to the kernel can be used in conjunction with the MPU. The base address of a region must be aligned to the region size, otherwise behavior is unpredictable and region sizes can only be specified as a power-of-two. To simplify the satisfaction of these requirements this implementation currently enforces that all memory is contiguous from PHYS_OFFSET, merging banks that are contiguous but passed in separately. The functions are added in this patch but wired in to the boot process later in the series. Signed-off-by: Jonathan Austin <jonathan.austin@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> CC: Hyok S. Choi <hyok.choi@samsung.com>
This commit is contained in:
Jonathan Austin
parent
67c9845bea
commit
5ad7dcbe40
@ -8,6 +8,7 @@
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#include <linux/pagemap.h>
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#include <linux/io.h>
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#include <linux/memblock.h>
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#include <linux/kernel.h>
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#include <asm/cacheflush.h>
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#include <asm/sections.h>
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@ -15,9 +16,257 @@
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#include <asm/setup.h>
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#include <asm/traps.h>
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#include <asm/mach/arch.h>
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#include <asm/cputype.h>
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#include <asm/mpu.h>
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#include "mm.h"
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#ifdef CONFIG_ARM_MPU
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struct mpu_rgn_info mpu_rgn_info;
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/* Region number */
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static void rgnr_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c2, 0" : : "r" (v));
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}
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/* Data-side / unified region attributes */
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/* Region access control register */
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static void dracr_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c1, 4" : : "r" (v));
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}
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/* Region size register */
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static void drsr_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c1, 2" : : "r" (v));
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}
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/* Region base address register */
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static void drbar_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c1, 0" : : "r" (v));
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}
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static u32 drbar_read(void)
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{
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u32 v;
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asm("mrc p15, 0, %0, c6, c1, 0" : "=r" (v));
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return v;
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}
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/* Optional instruction-side region attributes */
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/* I-side Region access control register */
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static void iracr_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c1, 5" : : "r" (v));
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}
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/* I-side Region size register */
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static void irsr_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c1, 3" : : "r" (v));
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}
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/* I-side Region base address register */
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static void irbar_write(u32 v)
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{
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asm("mcr p15, 0, %0, c6, c1, 1" : : "r" (v));
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}
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static unsigned long irbar_read(void)
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{
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unsigned long v;
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asm("mrc p15, 0, %0, c6, c1, 1" : "=r" (v));
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return v;
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}
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/* MPU initialisation functions */
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void __init sanity_check_meminfo_mpu(void)
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{
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int i;
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struct membank *bank = meminfo.bank;
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phys_addr_t phys_offset = PHYS_OFFSET;
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phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size;
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/* Initially only use memory continuous from PHYS_OFFSET */
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if (bank_phys_start(&bank[0]) != phys_offset)
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panic("First memory bank must be contiguous from PHYS_OFFSET");
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/* Banks have already been sorted by start address */
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for (i = 1; i < meminfo.nr_banks; i++) {
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if (bank[i].start <= bank_phys_end(&bank[0]) &&
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bank_phys_end(&bank[i]) > bank_phys_end(&bank[0])) {
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bank[0].size = bank_phys_end(&bank[i]) - bank[0].start;
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} else {
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pr_notice("Ignoring RAM after 0x%.8lx. "
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"First non-contiguous (ignored) bank start: 0x%.8lx\n",
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(unsigned long)bank_phys_end(&bank[0]),
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(unsigned long)bank_phys_start(&bank[i]));
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break;
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}
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}
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/* All contiguous banks are now merged in to the first bank */
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meminfo.nr_banks = 1;
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specified_mem_size = bank[0].size;
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/*
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* MPU has curious alignment requirements: Size must be power of 2, and
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* region start must be aligned to the region size
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*/
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if (phys_offset != 0)
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pr_info("PHYS_OFFSET != 0 => MPU Region size constrained by alignment requirements\n");
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/*
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* Maximum aligned region might overflow phys_addr_t if phys_offset is
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* 0. Hence we keep everything below 4G until we take the smaller of
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* the aligned_region_size and rounded_mem_size, one of which is
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* guaranteed to be smaller than the maximum physical address.
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*/
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aligned_region_size = (phys_offset - 1) ^ (phys_offset);
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/* Find the max power-of-two sized region that fits inside our bank */
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rounded_mem_size = (1 << __fls(bank[0].size)) - 1;
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/* The actual region size is the smaller of the two */
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aligned_region_size = aligned_region_size < rounded_mem_size
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? aligned_region_size + 1
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: rounded_mem_size + 1;
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if (aligned_region_size != specified_mem_size)
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pr_warn("Truncating memory from 0x%.8lx to 0x%.8lx (MPU region constraints)",
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(unsigned long)specified_mem_size,
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(unsigned long)aligned_region_size);
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meminfo.bank[0].size = aligned_region_size;
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pr_debug("MPU Region from 0x%.8lx size 0x%.8lx (end 0x%.8lx))\n",
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(unsigned long)phys_offset,
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(unsigned long)aligned_region_size,
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(unsigned long)bank_phys_end(&bank[0]));
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}
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static int mpu_present(void)
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{
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return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7);
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}
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static int mpu_max_regions(void)
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{
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/*
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* We don't support a different number of I/D side regions so if we
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* have separate instruction and data memory maps then return
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* whichever side has a smaller number of supported regions.
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*/
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u32 dregions, iregions, mpuir;
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mpuir = read_cpuid(CPUID_MPUIR);
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dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION;
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/* Check for separate d-side and i-side memory maps */
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if (mpuir & MPUIR_nU)
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iregions = (mpuir & MPUIR_IREGION_SZMASK) >> MPUIR_IREGION;
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/* Use the smallest of the two maxima */
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return min(dregions, iregions);
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}
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static int mpu_iside_independent(void)
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{
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/* MPUIR.nU specifies whether there is *not* a unified memory map */
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return read_cpuid(CPUID_MPUIR) & MPUIR_nU;
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}
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static int mpu_min_region_order(void)
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{
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u32 drbar_result, irbar_result;
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/* We've kept a region free for this probing */
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rgnr_write(MPU_PROBE_REGION);
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isb();
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/*
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* As per ARM ARM, write 0xFFFFFFFC to DRBAR to find the minimum
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* region order
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*/
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drbar_write(0xFFFFFFFC);
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drbar_result = irbar_result = drbar_read();
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drbar_write(0x0);
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/* If the MPU is non-unified, we use the larger of the two minima*/
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if (mpu_iside_independent()) {
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irbar_write(0xFFFFFFFC);
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irbar_result = irbar_read();
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irbar_write(0x0);
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}
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isb(); /* Ensure that MPU region operations have completed */
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/* Return whichever result is larger */
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return __ffs(max(drbar_result, irbar_result));
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}
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static int mpu_setup_region(unsigned int number, phys_addr_t start,
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unsigned int size_order, unsigned int properties)
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{
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u32 size_data;
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/* We kept a region free for probing resolution of MPU regions*/
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if (number > mpu_max_regions() || number == MPU_PROBE_REGION)
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return -ENOENT;
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if (size_order > 32)
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return -ENOMEM;
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if (size_order < mpu_min_region_order())
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return -ENOMEM;
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/* Writing N to bits 5:1 (RSR_SZ) specifies region size 2^N+1 */
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size_data = ((size_order - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN;
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dsb(); /* Ensure all previous data accesses occur with old mappings */
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rgnr_write(number);
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isb();
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drbar_write(start);
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dracr_write(properties);
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isb(); /* Propagate properties before enabling region */
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drsr_write(size_data);
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/* Check for independent I-side registers */
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if (mpu_iside_independent()) {
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irbar_write(start);
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iracr_write(properties);
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isb();
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irsr_write(size_data);
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}
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isb();
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/* Store region info (we treat i/d side the same, so only store d) */
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mpu_rgn_info.rgns[number].dracr = properties;
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mpu_rgn_info.rgns[number].drbar = start;
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mpu_rgn_info.rgns[number].drsr = size_data;
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return 0;
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}
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/*
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* Set up default MPU regions, doing nothing if there is no MPU
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*/
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void __init mpu_setup(void)
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{
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int region_err;
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if (!mpu_present())
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return;
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region_err = mpu_setup_region(MPU_RAM_REGION, PHYS_OFFSET,
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ilog2(meminfo.bank[0].size),
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MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL);
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if (region_err) {
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panic("MPU region initialization failure! %d", region_err);
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} else {
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pr_info("Using ARMv7 PMSA Compliant MPU. "
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"Region independence: %s, Max regions: %d\n",
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mpu_iside_independent() ? "Yes" : "No",
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mpu_max_regions());
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}
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}
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#endif /* CONFIG_ARM_MPU */
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void __init arm_mm_memblock_reserve(void)
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{
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#ifndef CONFIG_CPU_V7M
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