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perf/x86/intel/P4: Robistify P4 PMU types
Linus found, while extending integer type extension checks in the sparse static code checker, various fragile patterns of mixed signed/unsigned 64-bit/32-bit integer use in perf_events_p4.c. The relevant hardware register ABI is 64 bit wide on 32-bit kernels as well, so clean it all up a bit, remove unnecessary casts, and make sure we use 64-bit unsigned integers in these places. [ Unfortunately this patch was not tested on real P4 hardware, those are pretty rare already. If this patch causes any problems on P4 hardware then please holler ... ] Reported-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: David Miller <davem@davemloft.net> Cc: Theodore Ts'o <tytso@mit.edu> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Cyrill Gorcunov <gorcunov@gmail.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/20130424072630.GB1780@gmail.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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Ingo Molnar
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@ -24,45 +24,45 @@
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#define ARCH_P4_CNTRVAL_MASK ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)
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#define ARCH_P4_UNFLAGGED_BIT ((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1))
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#define P4_ESCR_EVENT_MASK 0x7e000000U
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#define P4_ESCR_EVENT_MASK 0x7e000000ULL
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#define P4_ESCR_EVENT_SHIFT 25
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#define P4_ESCR_EVENTMASK_MASK 0x01fffe00U
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#define P4_ESCR_EVENTMASK_MASK 0x01fffe00ULL
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#define P4_ESCR_EVENTMASK_SHIFT 9
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#define P4_ESCR_TAG_MASK 0x000001e0U
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#define P4_ESCR_TAG_MASK 0x000001e0ULL
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#define P4_ESCR_TAG_SHIFT 5
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#define P4_ESCR_TAG_ENABLE 0x00000010U
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#define P4_ESCR_T0_OS 0x00000008U
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#define P4_ESCR_T0_USR 0x00000004U
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#define P4_ESCR_T1_OS 0x00000002U
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#define P4_ESCR_T1_USR 0x00000001U
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#define P4_ESCR_TAG_ENABLE 0x00000010ULL
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#define P4_ESCR_T0_OS 0x00000008ULL
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#define P4_ESCR_T0_USR 0x00000004ULL
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#define P4_ESCR_T1_OS 0x00000002ULL
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#define P4_ESCR_T1_USR 0x00000001ULL
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#define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT)
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#define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT)
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#define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT)
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#define P4_CCCR_OVF 0x80000000U
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#define P4_CCCR_CASCADE 0x40000000U
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#define P4_CCCR_OVF_PMI_T0 0x04000000U
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#define P4_CCCR_OVF_PMI_T1 0x08000000U
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#define P4_CCCR_FORCE_OVF 0x02000000U
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#define P4_CCCR_EDGE 0x01000000U
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#define P4_CCCR_THRESHOLD_MASK 0x00f00000U
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#define P4_CCCR_OVF 0x80000000ULL
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#define P4_CCCR_CASCADE 0x40000000ULL
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#define P4_CCCR_OVF_PMI_T0 0x04000000ULL
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#define P4_CCCR_OVF_PMI_T1 0x08000000ULL
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#define P4_CCCR_FORCE_OVF 0x02000000ULL
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#define P4_CCCR_EDGE 0x01000000ULL
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#define P4_CCCR_THRESHOLD_MASK 0x00f00000ULL
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#define P4_CCCR_THRESHOLD_SHIFT 20
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#define P4_CCCR_COMPLEMENT 0x00080000U
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#define P4_CCCR_COMPARE 0x00040000U
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#define P4_CCCR_ESCR_SELECT_MASK 0x0000e000U
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#define P4_CCCR_COMPLEMENT 0x00080000ULL
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#define P4_CCCR_COMPARE 0x00040000ULL
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#define P4_CCCR_ESCR_SELECT_MASK 0x0000e000ULL
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#define P4_CCCR_ESCR_SELECT_SHIFT 13
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#define P4_CCCR_ENABLE 0x00001000U
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#define P4_CCCR_THREAD_SINGLE 0x00010000U
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#define P4_CCCR_THREAD_BOTH 0x00020000U
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#define P4_CCCR_THREAD_ANY 0x00030000U
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#define P4_CCCR_RESERVED 0x00000fffU
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#define P4_CCCR_ENABLE 0x00001000ULL
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#define P4_CCCR_THREAD_SINGLE 0x00010000ULL
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#define P4_CCCR_THREAD_BOTH 0x00020000ULL
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#define P4_CCCR_THREAD_ANY 0x00030000ULL
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#define P4_CCCR_RESERVED 0x00000fffULL
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#define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT)
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#define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT)
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#define P4_GEN_ESCR_EMASK(class, name, bit) \
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class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT)
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class##__##name = ((1ULL << bit) << P4_ESCR_EVENTMASK_SHIFT)
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#define P4_ESCR_EMASK_BIT(class, name) class##__##name
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/*
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@ -107,7 +107,7 @@
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* P4_PEBS_CONFIG_MASK and related bits on
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* modification.)
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*/
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#define P4_CONFIG_ALIASABLE (1 << 9)
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#define P4_CONFIG_ALIASABLE (1ULL << 9)
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/*
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* The bits we allow to pass for RAW events
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@ -784,17 +784,17 @@ enum P4_ESCR_EMASKS {
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* Note we have UOP and PEBS bits reserved for now
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* just in case if we will need them once
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*/
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#define P4_PEBS_CONFIG_ENABLE (1 << 7)
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#define P4_PEBS_CONFIG_UOP_TAG (1 << 8)
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#define P4_PEBS_CONFIG_METRIC_MASK 0x3f
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#define P4_PEBS_CONFIG_MASK 0xff
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#define P4_PEBS_CONFIG_ENABLE (1ULL << 7)
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#define P4_PEBS_CONFIG_UOP_TAG (1ULL << 8)
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#define P4_PEBS_CONFIG_METRIC_MASK 0x3FLL
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#define P4_PEBS_CONFIG_MASK 0xFFLL
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/*
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* mem: Only counters MSR_IQ_COUNTER4 (16) and
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* MSR_IQ_COUNTER5 (17) are allowed for PEBS sampling
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*/
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#define P4_PEBS_ENABLE 0x02000000U
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#define P4_PEBS_ENABLE_UOP_TAG 0x01000000U
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#define P4_PEBS_ENABLE 0x02000000ULL
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#define P4_PEBS_ENABLE_UOP_TAG 0x01000000ULL
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#define p4_config_unpack_metric(v) (((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK)
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#define p4_config_unpack_pebs(v) (((u64)(v)) & P4_PEBS_CONFIG_MASK)
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@ -895,8 +895,8 @@ static void p4_pmu_disable_pebs(void)
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* So at moment let leave metrics turned on forever -- it's
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* ok for now but need to be revisited!
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*
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* (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, (u64)0);
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* (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT, (u64)0);
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* (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, 0);
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* (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT, 0);
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*/
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}
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@ -910,8 +910,7 @@ static inline void p4_pmu_disable_event(struct perf_event *event)
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* asserted again and again
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*/
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(void)wrmsrl_safe(hwc->config_base,
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(u64)(p4_config_unpack_cccr(hwc->config)) &
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~P4_CCCR_ENABLE & ~P4_CCCR_OVF & ~P4_CCCR_RESERVED);
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p4_config_unpack_cccr(hwc->config) & ~P4_CCCR_ENABLE & ~P4_CCCR_OVF & ~P4_CCCR_RESERVED);
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}
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static void p4_pmu_disable_all(void)
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@ -957,7 +956,7 @@ static void p4_pmu_enable_event(struct perf_event *event)
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u64 escr_addr, cccr;
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bind = &p4_event_bind_map[idx];
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escr_addr = (u64)bind->escr_msr[thread];
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escr_addr = bind->escr_msr[thread];
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/*
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* - we dont support cascaded counters yet
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