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Merge branch 'sh_eth-reg-defs'
Sergey Shtylyov says: ==================== sh_eth: Improve the register/bit definitions in the Ether driver Here are 4 patches against DaveM's 'net-next' repo. Mainly I'm renaming the register *enum* tags/entries to match the SoC manuals,and also moving the RX-TX descriptor *enum*s closer to the corresponding *struct*s... ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
5ab6f96a12
@ -560,7 +560,7 @@ static struct sh_eth_cpu_data r7s72100_data = {
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EESR_TDE,
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.fdr_value = 0x0000070f,
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.trscer_err_mask = DESC_I_RINT8 | DESC_I_RINT5,
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.trscer_err_mask = TRSCER_RMAFCE | TRSCER_RRFCE,
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.no_psr = 1,
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.apr = 1,
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@ -701,7 +701,7 @@ static struct sh_eth_cpu_data rcar_gen2_data = {
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EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
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.fdr_value = 0x00000f0f,
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.trscer_err_mask = DESC_I_RINT8,
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.trscer_err_mask = TRSCER_RMAFCE,
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.apr = 1,
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.mpr = 1,
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@ -782,7 +782,7 @@ static struct sh_eth_cpu_data r7s9210_data = {
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.fdr_value = 0x0000070f,
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.trscer_err_mask = DESC_I_RINT8 | DESC_I_RINT5,
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.trscer_err_mask = TRSCER_RMAFCE | TRSCER_RRFCE,
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.apr = 1,
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.mpr = 1,
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@ -1094,7 +1094,7 @@ static struct sh_eth_cpu_data sh771x_data = {
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EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
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EESIPR_PREIP | EESIPR_CERFIP,
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.trscer_err_mask = DESC_I_RINT8,
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.trscer_err_mask = TRSCER_RMAFCE,
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.tsu = 1,
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.dual_port = 1,
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@ -1749,7 +1749,7 @@ static void sh_eth_emac_interrupt(struct net_device *ndev)
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link_stat = sh_eth_read(ndev, PSR);
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if (mdp->ether_link_active_low)
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link_stat = ~link_stat;
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if (!(link_stat & PHY_ST_LINK)) {
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if (!(link_stat & PSR_LMON)) {
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sh_eth_rcv_snd_disable(ndev);
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} else {
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/* Link Up */
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@ -171,7 +171,7 @@ enum GECMR_BIT {
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};
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/* EDMR */
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enum DMAC_M_BIT {
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enum EDMR_BIT {
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EDMR_NBST = 0x80,
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EDMR_EL = 0x40, /* Litte endian */
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EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
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@ -180,13 +180,13 @@ enum DMAC_M_BIT {
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};
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/* EDTRR */
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enum DMAC_T_BIT {
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enum EDTRR_BIT {
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EDTRR_TRNS_GETHER = 0x03,
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EDTRR_TRNS_ETHER = 0x01,
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};
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/* EDRRR */
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enum EDRRR_R_BIT {
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enum EDRRR_BIT {
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EDRRR_R = 0x01,
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};
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@ -208,7 +208,7 @@ enum PIR_BIT {
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};
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/* PSR */
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enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
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enum PSR_BIT { PSR_LMON = 0x01, };
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/* EESR */
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enum EESR_BIT {
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@ -288,27 +288,6 @@ enum EESIPR_BIT {
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EESIPR_CERFIP = 0x00000001,
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};
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/* Receive descriptor 0 bits */
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enum RD_STS_BIT {
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RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
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RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
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RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
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RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
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RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
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RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
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RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
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RD_RFS1 = 0x00000001,
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};
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#define RDF1ST RD_RFP1
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#define RDFEND RD_RFP0
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#define RD_RFP (RD_RFP1|RD_RFP0)
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/* Receive descriptor 1 bits */
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enum RD_LEN_BIT {
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RD_RFL = 0x0000ffff, /* receive frame length */
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RD_RBL = 0xffff0000, /* receive buffer length */
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};
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/* FCFTR */
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enum FCFTR_BIT {
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FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
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@ -318,28 +297,13 @@ enum FCFTR_BIT {
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#define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
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#define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
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/* Transmit descriptor 0 bits */
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enum TD_STS_BIT {
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TD_TACT = 0x80000000, TD_TDLE = 0x40000000,
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TD_TFP1 = 0x20000000, TD_TFP0 = 0x10000000,
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TD_TFE = 0x08000000, TD_TWBI = 0x04000000,
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};
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#define TDF1ST TD_TFP1
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#define TDFEND TD_TFP0
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#define TD_TFP (TD_TFP1|TD_TFP0)
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/* Transmit descriptor 1 bits */
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enum TD_LEN_BIT {
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TD_TBL = 0xffff0000, /* transmit buffer length */
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};
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/* RMCR */
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enum RMCR_BIT {
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RMCR_RNC = 0x00000001,
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};
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/* ECMR */
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enum FELIC_MODE_BIT {
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enum ECMR_BIT {
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ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
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ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
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ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
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@ -350,7 +314,7 @@ enum FELIC_MODE_BIT {
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};
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/* ECSR */
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enum ECSR_STATUS_BIT {
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enum ECSR_BIT {
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ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
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ECSR_LCHNG = 0x04,
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ECSR_MPD = 0x02, ECSR_ICD = 0x01,
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@ -360,7 +324,7 @@ enum ECSR_STATUS_BIT {
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ECSR_ICD | ECSIPR_MPDIP)
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/* ECSIPR */
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enum ECSIPR_STATUS_MASK_BIT {
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enum ECSIPR_BIT {
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ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
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ECSIPR_LCHNGIP = 0x04,
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ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
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@ -380,14 +344,20 @@ enum MPR_BIT {
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};
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/* TRSCER */
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enum DESC_I_BIT {
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DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
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DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
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DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
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DESC_I_RINT1 = 0x0001,
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enum TRSCER_BIT {
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TRSCER_CNDCE = 0x00000800,
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TRSCER_DLCCE = 0x00000400,
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TRSCER_CDCE = 0x00000200,
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TRSCER_TROCE = 0x00000100,
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TRSCER_RMAFCE = 0x00000080,
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TRSCER_RRFCE = 0x00000010,
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TRSCER_RTLFCE = 0x00000008,
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TRSCER_RTSFCE = 0x00000004,
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TRSCER_PRECE = 0x00000002,
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TRSCER_CERFCE = 0x00000001,
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};
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#define DEFAULT_TRSCER_ERR_MASK (DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2)
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#define DEFAULT_TRSCER_ERR_MASK (TRSCER_RMAFCE | TRSCER_RRFCE | TRSCER_CDCE)
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/* RPADIR */
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enum RPADIR_BIT {
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@ -445,6 +415,24 @@ struct sh_eth_txdesc {
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u32 pad0; /* padding data */
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} __aligned(2) __packed;
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/* Transmit descriptor 0 bits */
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enum TD_STS_BIT {
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TD_TACT = 0x80000000,
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TD_TDLE = 0x40000000,
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TD_TFP1 = 0x20000000,
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TD_TFP0 = 0x10000000,
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TD_TFE = 0x08000000,
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TD_TWBI = 0x04000000,
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};
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#define TDF1ST TD_TFP1
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#define TDFEND TD_TFP0
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#define TD_TFP (TD_TFP1 | TD_TFP0)
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/* Transmit descriptor 1 bits */
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enum TD_LEN_BIT {
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TD_TBL = 0xffff0000, /* transmit buffer length */
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};
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/* The sh ether Rx buffer descriptors.
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* This structure should be 20 bytes.
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*/
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@ -455,6 +443,34 @@ struct sh_eth_rxdesc {
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u32 pad0; /* padding data */
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} __aligned(2) __packed;
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/* Receive descriptor 0 bits */
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enum RD_STS_BIT {
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RD_RACT = 0x80000000,
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RD_RDLE = 0x40000000,
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RD_RFP1 = 0x20000000,
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RD_RFP0 = 0x10000000,
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RD_RFE = 0x08000000,
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RD_RFS10 = 0x00000200,
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RD_RFS9 = 0x00000100,
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RD_RFS8 = 0x00000080,
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RD_RFS7 = 0x00000040,
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RD_RFS6 = 0x00000020,
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RD_RFS5 = 0x00000010,
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RD_RFS4 = 0x00000008,
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RD_RFS3 = 0x00000004,
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RD_RFS2 = 0x00000002,
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RD_RFS1 = 0x00000001,
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};
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#define RDF1ST RD_RFP1
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#define RDFEND RD_RFP0
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#define RD_RFP (RD_RFP1 | RD_RFP0)
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/* Receive descriptor 1 bits */
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enum RD_LEN_BIT {
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RD_RFL = 0x0000ffff, /* receive frame length */
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RD_RBL = 0xffff0000, /* receive buffer length */
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};
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/* This structure is used by each CPU dependency handling. */
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struct sh_eth_cpu_data {
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/* mandatory functions */
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