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clk: renesas: r8a779g0: Add PCIe clocks

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Add the PCIe module clocks, which are used by the PCIe modules on the
Renesas R-Car V4H (R8A779G0) SoC.  Note that the following descriptions
in the hardware manual Rev.0.81 about the PCIe module clocks are
incorrect:

    9.2.1.7 Software Reset Register 6 (SRCR6)
    9.2.1.12 Software Reset Register 11 (SRCR11)
    9.2.3.7 Module Stop Control Register 6 (MSTPCR6)

Please refer to Figures 104.3[ab] instead.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231114122252.2266799-1-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Yoshihiro Shimoda 2023-11-14 21:22:52 +09:00 committed by Geert Uytterhoeven
parent f154ef08ca
commit 5ab16198b4
1 changed files with 2 additions and 0 deletions
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2
drivers/clk/renesas/r8a779g0-cpg-mssr.c
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@ -192,6 +192,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
DEF_MOD("msi3", 621, R8A779G0_CLK_MSO),
DEF_MOD("msi4", 622, R8A779G0_CLK_MSO),
DEF_MOD("msi5", 623, R8A779G0_CLK_MSO),
DEF_MOD("pciec0", 624, R8A779G0_CLK_S0D2_HSC),
DEF_MOD("pscie1", 625, R8A779G0_CLK_S0D2_HSC),
DEF_MOD("pwm", 628, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("rpc-if", 629, R8A779G0_CLK_RPCD2),
DEF_MOD("scif0", 702, R8A779G0_CLK_SASYNCPERD4),