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First fixes batch for AT91 on 4.0:

Browse Source 
- PM slowclock fixes for DDR and timeouts
 - fix some DT entries
 - little defconfig updates
 - the removal of a harmful watchdog option + its detailed documentation
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQEcBAABAgAGBQJU9uKaAAoJEAf03oE53VmQrT4IAID5RZZLycH65MfI2SWs5jHJ
 riXpp2ByX2YMZhBV7Y+jSJcdty0zdZFXAm3cME8YtHSHFNW87y3U90BhL1JTwFh8
 Rlk45xxauRmiH5R+0haBIavt+ZFHB8QOgmAE+xa4Vc/qBiry6HSgWVldk3yiai5j
 Mnq/+UpeL7mSlcn9kFkbVVOkDiP2tRoITU0z780tBgywbUQEluNZan4MfjSaknzP
 GEwmN74Z6QPUxhqc1Z1ACU84ozYcLYaiMksNXrTch0+dLz91MIRl6Eqb53XhJEK3
 P8ysCj16UBgX2JuuYWBGkxrZ1Brl0Lj5075JrM+He0T/XRsLTChb+9rQ14QrKno=
 =YpBm
 -----END PGP SIGNATURE-----

Merge tag 'at91-fixes' into at91-4.1-multiplatform

First fixes batch for AT91 on 4.0:
- PM slowclock fixes for DDR and timeouts
- fix some DT entries
- little defconfig updates
- the removal of a harmful watchdog option + its detailed documentation
This commit is contained in:
Nicolas Ferre 2015-03-16 18:09:27 +01:00
commit 59f5f7d054
14 changed files with 64 additions and 59 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
View File

@ -26,6 +26,11 @@ Optional properties:
- atmel,disable : Should be present if you want to disable the watchdog.
- atmel,idle-halt : Should be present if you want to stop the watchdog when
entering idle state.
CAUTION: This property should be used with care, it actually makes the
watchdog not counting when the CPU is in idle state, therefore the
watchdog reset time depends on mean CPU usage and will not reset at all
if the CPU stop working while it is in idle state, which is probably
not what you want.
- atmel,dbg-halt : Should be present if you want to stop the watchdog when
entering debug state.

5
arch/arm/boot/dts/at91sam9260.dtsi
View File

@ -494,12 +494,12 @@
pinctrl_usart3_rts: usart3_rts-0 {
atmel,pins =
<AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC8 periph B */
<AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_usart3_cts: usart3_cts-0 {
atmel,pins =
<AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC10 periph B */
<AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
@ -976,7 +976,6 @@
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
atmel,idle-halt;
status = "disabled";
};

3
arch/arm/boot/dts/at91sam9263.dtsi
View File

@ -69,7 +69,7 @@
sram1: sram@00500000 {
compatible = "mmio-sram";
reg = <0x00300000 0x4000>;
reg = <0x00500000 0x4000>;
};
ahb {
@ -905,7 +905,6 @@
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
atmel,idle-halt;
status = "disabled";
};

1
arch/arm/boot/dts/at91sam9g45.dtsi
View File

@ -1116,7 +1116,6 @@
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
atmel,idle-halt;
status = "disabled";
};

1
arch/arm/boot/dts/at91sam9n12.dtsi
View File

@ -894,7 +894,6 @@
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
atmel,idle-halt;
status = "disabled";
};

1
arch/arm/boot/dts/at91sam9x5.dtsi
View File

@ -1130,7 +1130,6 @@
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
atmel,idle-halt;
status = "disabled";
};

1
arch/arm/boot/dts/sama5d3.dtsi
View File

@ -1248,7 +1248,6 @@
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
atmel,idle-halt;
status = "disabled";
};

1
arch/arm/boot/dts/sama5d4.dtsi
View File

@ -66,6 +66,7 @@
gpio4 = &pioE;
tcb0 = &tcb0;
tcb1 = &tcb1;
i2c0 = &i2c0;
i2c2 = &i2c2;
};
cpus {

1
arch/arm/configs/at91_dt_defconfig
View File

@ -70,6 +70,7 @@ CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_ARM_AT91_ETHER=y
CONFIG_MACB=y
# CONFIG_NET_VENDOR_BROADCOM is not set
CONFIG_DM9000=y

2
arch/arm/configs/sama5_defconfig
View File

@ -3,8 +3,6 @@
CONFIG_SYSVIPC=y
CONFIG_IRQ_DOMAIN_DEBUG=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y

22
arch/arm/mach-at91/pm.c
View File

@ -270,37 +270,35 @@ static void __init at91_pm_sram_init(void)
phys_addr_t sram_pbase;
unsigned long sram_base;
struct device_node *node;
struct platform_device *pdev;
struct platform_device *pdev = NULL;
node = of_find_compatible_node(NULL, NULL, "mmio-sram");
if (!node) {
pr_warn("%s: failed to find sram node!\n", __func__);
return;
for_each_compatible_node(node, NULL, "mmio-sram") {
pdev = of_find_device_by_node(node);
if (pdev) {
of_node_put(node);
break;
}
}
pdev = of_find_device_by_node(node);
if (!pdev) {
pr_warn("%s: failed to find sram device!\n", __func__);
goto put_node;
return;
}
sram_pool = dev_get_gen_pool(&pdev->dev);
if (!sram_pool) {
pr_warn("%s: sram pool unavailable!\n", __func__);
goto put_node;
return;
}
sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz);
if (!sram_base) {
pr_warn("%s: unable to alloc ocram!\n", __func__);
goto put_node;
return;
}
sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false);
put_node:
of_node_put(node);
}
#endif

2
arch/arm/mach-at91/pm.h
View File

@ -44,7 +44,7 @@ static inline void at91rm9200_standby(void)
" mcr p15, 0, %0, c7, c0, 4\n\t"
" str %5, [%1, %2]"
:
: "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
: "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
"r" (1), "r" (AT91RM9200_SDRAMC_SRR),
"r" (lpr));
}

76
arch/arm/mach-at91/pm_slowclock.S
View File

@ -25,11 +25,6 @@
*/
#undef SLOWDOWN_MASTER_CLOCK
#define MCKRDY_TIMEOUT 1000
#define MOSCRDY_TIMEOUT 1000
#define PLLALOCK_TIMEOUT 1000
#define PLLBLOCK_TIMEOUT 1000
pmc .req r0
sdramc .req r1
ramc1 .req r2
@ -41,56 +36,36 @@ tmp2 .req r5
* Wait until master clock is ready (after switching master clock source)
*/
.macro wait_mckrdy
mov tmp2, #MCKRDY_TIMEOUT
1: sub tmp2, tmp2, #1
cmp tmp2, #0
beq 2f
ldr tmp1, [pmc, #AT91_PMC_SR]
1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_MCKRDY
beq 1b
2:
.endm
/*
* Wait until master oscillator has stabilized.
*/
.macro wait_moscrdy
mov tmp2, #MOSCRDY_TIMEOUT
1: sub tmp2, tmp2, #1
cmp tmp2, #0
beq 2f
ldr tmp1, [pmc, #AT91_PMC_SR]
1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_MOSCS
beq 1b
2:
.endm
/*
* Wait until PLLA has locked.
*/
.macro wait_pllalock
mov tmp2, #PLLALOCK_TIMEOUT
1: sub tmp2, tmp2, #1
cmp tmp2, #0
beq 2f
ldr tmp1, [pmc, #AT91_PMC_SR]
1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_LOCKA
beq 1b
2:
.endm
/*
* Wait until PLLB has locked.
*/
.macro wait_pllblock
mov tmp2, #PLLBLOCK_TIMEOUT
1: sub tmp2, tmp2, #1
cmp tmp2, #0
beq 2f
ldr tmp1, [pmc, #AT91_PMC_SR]
1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_LOCKB
beq 1b
2:
.endm
.text
@ -134,6 +109,16 @@ ddr_sr_enable:
cmp memctrl, #AT91_MEMCTRL_DDRSDR
bne sdr_sr_enable
/* LPDDR1 --> force DDR2 mode during self-refresh */
ldr tmp1, [sdramc, #AT91_DDRSDRC_MDR]
str tmp1, .saved_sam9_mdr
bic tmp1, tmp1, #~AT91_DDRSDRC_MD
cmp tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR
ldreq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
biceq tmp1, tmp1, #AT91_DDRSDRC_MD
orreq tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2
streq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
/* prepare for DDRAM self-refresh mode */
ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
str tmp1, .saved_sam9_lpr
@ -142,14 +127,26 @@ ddr_sr_enable:
/* figure out if we use the second ram controller */
cmp ramc1, #0
ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
strne tmp2, .saved_sam9_lpr1
bicne tmp2, #AT91_DDRSDRC_LPCB
orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
beq ddr_no_2nd_ctrl
ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
str tmp2, .saved_sam9_mdr1
bic tmp2, tmp2, #~AT91_DDRSDRC_MD
cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
biceq tmp2, tmp2, #AT91_DDRSDRC_MD
orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
str tmp2, .saved_sam9_lpr1
bic tmp2, #AT91_DDRSDRC_LPCB
orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
/* Enable DDRAM self-refresh mode */
str tmp2, [ramc1, #AT91_DDRSDRC_LPR]
ddr_no_2nd_ctrl:
str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
b sdr_sr_done
@ -280,12 +277,17 @@ sdr_sr_done:
*/
cmp memctrl, #AT91_MEMCTRL_DDRSDR
bne sdr_en_restore
/* Restore MDR in case of LPDDR1 */
ldr tmp1, .saved_sam9_mdr
str tmp1, [sdramc, #AT91_DDRSDRC_MDR]
/* Restore LPR on AT91 with DDRAM */
ldr tmp1, .saved_sam9_lpr
str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
/* if we use the second ram controller */
cmp ramc1, #0
ldrne tmp2, .saved_sam9_mdr1
strne tmp2, [ramc1, #AT91_DDRSDRC_MDR]
ldrne tmp2, .saved_sam9_lpr1
strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
@ -319,5 +321,11 @@ ram_restored:
.saved_sam9_lpr1:
.word 0
.saved_sam9_mdr:
.word 0
.saved_sam9_mdr1:
.word 0
ENTRY(at91_slow_clock_sz)
.word .-at91_slow_clock

2
include/soc/at91/at91sam9_ddrsdr.h
View File

@ -92,7 +92,7 @@
#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
#define AT91_DDRSDRC_MD (7 << 0) /* Memory Device Type */
#define AT91_DDRSDRC_MD_SDR 0
#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3