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PS3: gelic: code cleanup
Code cleanup: - Use appropriate prefixes for names instead of fixed 'gelic_net' so that objects of the functions, variables and constants can be estimated. - Remove definitions for IPSec offload to the gelic hardware. This functionality is never supported on PS3. - Group constants with enum. - Use bitwise constants for interrupt status, instead of bit numbers to eliminate shift operations. - Style fixes. Signed-off-by: Masakazu Mokuno <mokuno@sm.sony.co.jp> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Masakazu Mokuno
Jeff Garzik
parent
100e1d8919
commit
59e973277c
File diff suppressed because it is too large
Load Diff
@ -43,131 +43,170 @@
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#define GELIC_NET_VLAN_MAX 4
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#define GELIC_NET_MC_COUNT_MAX 32 /* multicast address list */
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enum gelic_net_int0_status {
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GELIC_NET_GDTDCEINT = 24,
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GELIC_NET_GRFANMINT = 28,
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};
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/* virtual interrupt status register bits */
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/* INT1 */
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#define GELIC_CARD_TX_RAM_FULL_ERR 0x0000000000000001L
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#define GELIC_CARD_RX_RAM_FULL_ERR 0x0000000000000002L
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#define GELIC_CARD_TX_SHORT_FRAME_ERR 0x0000000000000004L
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#define GELIC_CARD_TX_INVALID_DESCR_ERR 0x0000000000000008L
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#define GELIC_CARD_RX_FIFO_FULL_ERR 0x0000000000002000L
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#define GELIC_CARD_RX_DESCR_CHAIN_END 0x0000000000004000L
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#define GELIC_CARD_RX_INVALID_DESCR_ERR 0x0000000000008000L
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#define GELIC_CARD_TX_RESPONCE_ERR 0x0000000000010000L
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#define GELIC_CARD_RX_RESPONCE_ERR 0x0000000000100000L
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#define GELIC_CARD_TX_PROTECTION_ERR 0x0000000000400000L
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#define GELIC_CARD_RX_PROTECTION_ERR 0x0000000004000000L
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#define GELIC_CARD_TX_TCP_UDP_CHECKSUM_ERR 0x0000000008000000L
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#define GELIC_CARD_PORT_STATUS_CHANGED 0x0000000020000000L
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/* INT 0 */
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#define GELIC_CARD_TX_FLAGGED_DESCR 0x0004000000000000L
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#define GELIC_CARD_RX_FLAGGED_DESCR 0x0040000000000000L
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#define GELIC_CARD_TX_TRANSFER_END 0x0080000000000000L
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#define GELIC_CARD_TX_DESCR_CHAIN_END 0x0100000000000000L
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#define GELIC_CARD_NUMBER_OF_RX_FRAME 0x1000000000000000L
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#define GELIC_CARD_ONE_TIME_COUNT_TIMER 0x4000000000000000L
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#define GELIC_CARD_FREE_RUN_COUNT_TIMER 0x8000000000000000L
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/* GHIINT1STS bits */
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enum gelic_net_int1_status {
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GELIC_NET_GDADCEINT = 14,
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};
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/* initial interrupt mask */
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#define GELIC_CARD_TXINT GELIC_CARD_TX_DESCR_CHAIN_END
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/* interrupt mask */
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#define GELIC_NET_TXINT (1L << (GELIC_NET_GDTDCEINT + 32))
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#define GELIC_NET_RXINT0 (1L << (GELIC_NET_GRFANMINT + 32))
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#define GELIC_NET_RXINT1 (1L << GELIC_NET_GDADCEINT)
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#define GELIC_NET_RXINT (GELIC_NET_RXINT0 | GELIC_NET_RXINT1)
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#define GELIC_CARD_RXINT (GELIC_CARD_RX_DESCR_CHAIN_END | \
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GELIC_CARD_NUMBER_OF_RX_FRAME)
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/* RX descriptor data_status bits */
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#define GELIC_NET_RXDMADU 0x80000000 /* destination MAC addr unknown */
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#define GELIC_NET_RXLSTFBF 0x40000000 /* last frame buffer */
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#define GELIC_NET_RXIPCHK 0x20000000 /* IP checksum performed */
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#define GELIC_NET_RXTCPCHK 0x10000000 /* TCP/UDP checksup performed */
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#define GELIC_NET_RXIPSPKT 0x08000000 /* IPsec packet */
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#define GELIC_NET_RXIPSAHPRT 0x04000000 /* IPsec AH protocol performed */
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#define GELIC_NET_RXIPSESPPRT 0x02000000 /* IPsec ESP protocol performed */
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#define GELIC_NET_RXSESPAH 0x01000000 /*
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* IPsec ESP protocol auth
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* performed
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*/
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enum gelic_descr_rx_status {
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GELIC_DESCR_RXDMADU = 0x80000000, /* destination MAC addr unknown */
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GELIC_DESCR_RXLSTFBF = 0x40000000, /* last frame buffer */
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GELIC_DESCR_RXIPCHK = 0x20000000, /* IP checksum performed */
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GELIC_DESCR_RXTCPCHK = 0x10000000, /* TCP/UDP checksup performed */
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GELIC_DESCR_RXWTPKT = 0x00C00000, /*
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* wakeup trigger packet
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* 01: Magic Packet (TM)
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* 10: ARP packet
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* 11: Multicast MAC addr
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*/
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GELIC_DESCR_RXVLNPKT = 0x00200000, /* VLAN packet */
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/* bit 20..16 reserved */
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GELIC_DESCR_RXRRECNUM = 0x0000ff00, /* reception receipt number */
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/* bit 7..0 reserved */
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};
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#define GELIC_NET_RXWTPKT 0x00C00000 /*
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* wakeup trigger packet
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* 01: Magic Packet (TM)
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* 10: ARP packet
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* 11: Multicast MAC addr
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*/
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#define GELIC_NET_RXVLNPKT 0x00200000 /* VLAN packet */
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/* bit 20..16 reserved */
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#define GELIC_NET_RXRRECNUM 0x0000ff00 /* reception receipt number */
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#define GELIC_NET_RXRRECNUM_SHIFT 8
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/* bit 7..0 reserved */
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#define GELIC_DESCR_DATA_STATUS_CHK_MASK \
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(GELIC_DESCR_RXIPCHK | GELIC_DESCR_RXTCPCHK)
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#define GELIC_NET_TXDESC_TAIL 0
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#define GELIC_NET_DATA_STATUS_CHK_MASK (GELIC_NET_RXIPCHK | GELIC_NET_RXTCPCHK)
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/* TX descriptor data_status bits */
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enum gelic_descr_tx_status {
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GELIC_DESCR_TX_TAIL = 0x00000001, /* gelic treated this
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* descriptor was end of
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* a tx frame
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*/
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};
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/* RX descriptor data_error bits */
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/* bit 31 reserved */
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#define GELIC_NET_RXALNERR 0x40000000 /* alignement error 10/100M */
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#define GELIC_NET_RXOVERERR 0x20000000 /* oversize error */
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#define GELIC_NET_RXRNTERR 0x10000000 /* Runt error */
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#define GELIC_NET_RXIPCHKERR 0x08000000 /* IP checksum error */
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#define GELIC_NET_RXTCPCHKERR 0x04000000 /* TCP/UDP checksum error */
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#define GELIC_NET_RXUMCHSP 0x02000000 /* unmatched sp on sp */
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#define GELIC_NET_RXUMCHSPI 0x01000000 /* unmatched SPI on SAD */
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#define GELIC_NET_RXUMCHSAD 0x00800000 /* unmatched SAD */
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#define GELIC_NET_RXIPSAHERR 0x00400000 /* auth error on AH protocol
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* processing */
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#define GELIC_NET_RXIPSESPAHERR 0x00200000 /* auth error on ESP protocol
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* processing */
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#define GELIC_NET_RXDRPPKT 0x00100000 /* drop packet */
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#define GELIC_NET_RXIPFMTERR 0x00080000 /* IP packet format error */
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/* bit 18 reserved */
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#define GELIC_NET_RXDATAERR 0x00020000 /* IP packet format error */
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#define GELIC_NET_RXCALERR 0x00010000 /* cariier extension length
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* error */
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#define GELIC_NET_RXCREXERR 0x00008000 /* carrier extention error */
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#define GELIC_NET_RXMLTCST 0x00004000 /* multicast address frame */
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/* bit 13..0 reserved */
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#define GELIC_NET_DATA_ERROR_CHK_MASK \
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(GELIC_NET_RXIPCHKERR | GELIC_NET_RXTCPCHKERR)
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/* RX descriptor data error bits */
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enum gelic_descr_rx_error {
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/* bit 31 reserved */
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GELIC_DESCR_RXALNERR = 0x40000000, /* alignement error 10/100M */
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GELIC_DESCR_RXOVERERR = 0x20000000, /* oversize error */
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GELIC_DESCR_RXRNTERR = 0x10000000, /* Runt error */
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GELIC_DESCR_RXIPCHKERR = 0x08000000, /* IP checksum error */
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GELIC_DESCR_RXTCPCHKERR = 0x04000000, /* TCP/UDP checksum error */
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GELIC_DESCR_RXDRPPKT = 0x00100000, /* drop packet */
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GELIC_DESCR_RXIPFMTERR = 0x00080000, /* IP packet format error */
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/* bit 18 reserved */
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GELIC_DESCR_RXDATAERR = 0x00020000, /* IP packet format error */
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GELIC_DESCR_RXCALERR = 0x00010000, /* cariier extension length
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* error */
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GELIC_DESCR_RXCREXERR = 0x00008000, /* carrier extention error */
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GELIC_DESCR_RXMLTCST = 0x00004000, /* multicast address frame */
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/* bit 13..0 reserved */
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};
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#define GELIC_DESCR_DATA_ERROR_CHK_MASK \
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(GELIC_DESCR_RXIPCHKERR | GELIC_DESCR_RXTCPCHKERR)
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/* DMA command and status (RX and TX)*/
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enum gelic_descr_dma_status {
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GELIC_DESCR_DMA_COMPLETE = 0x00000000, /* used in tx */
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GELIC_DESCR_DMA_BUFFER_FULL = 0x00000000, /* used in rx */
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GELIC_DESCR_DMA_RESPONSE_ERROR = 0x10000000, /* used in rx, tx */
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GELIC_DESCR_DMA_PROTECTION_ERROR = 0x20000000, /* used in rx, tx */
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GELIC_DESCR_DMA_FRAME_END = 0x40000000, /* used in rx */
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GELIC_DESCR_DMA_FORCE_END = 0x50000000, /* used in rx, tx */
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GELIC_DESCR_DMA_CARDOWNED = 0xa0000000, /* used in rx, tx */
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GELIC_DESCR_DMA_NOT_IN_USE = 0xb0000000, /* any other value */
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};
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#define GELIC_DESCR_DMA_STAT_MASK (0xf0000000)
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/* tx descriptor command and status */
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#define GELIC_NET_DMAC_CMDSTAT_NOCS 0xa0080000 /* middle of frame */
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#define GELIC_NET_DMAC_CMDSTAT_TCPCS 0xa00a0000
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#define GELIC_NET_DMAC_CMDSTAT_UDPCS 0xa00b0000
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#define GELIC_NET_DMAC_CMDSTAT_END_FRAME 0x00040000 /* end of frame */
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enum gelic_descr_tx_dma_status {
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/* [19] */
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GELIC_DESCR_TX_DMA_IKE = 0x00080000, /* IPSEC off */
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/* [18] */
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GELIC_DESCR_TX_DMA_FRAME_TAIL = 0x00040000, /* last descriptor of
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* the packet
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*/
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/* [17..16] */
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GELIC_DESCR_TX_DMA_TCP_CHKSUM = 0x00020000, /* TCP packet */
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GELIC_DESCR_TX_DMA_UDP_CHKSUM = 0x00030000, /* UDP packet */
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GELIC_DESCR_TX_DMA_NO_CHKSUM = 0x00000000, /* no checksum */
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#define GELIC_NET_DMAC_CMDSTAT_RXDCEIS 0x00000002 /* descriptor chain end
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* interrupt status */
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#define GELIC_NET_DMAC_CMDSTAT_CHAIN_END 0x00000002 /* RXDCEIS:DMA stopped */
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#define GELIC_NET_DESCR_IND_PROC_SHIFT 28
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#define GELIC_NET_DESCR_IND_PROC_MASKO 0x0fffffff
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enum gelic_net_descr_status {
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GELIC_NET_DESCR_COMPLETE = 0x00, /* used in tx */
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GELIC_NET_DESCR_BUFFER_FULL = 0x00, /* used in rx */
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GELIC_NET_DESCR_RESPONSE_ERROR = 0x01, /* used in rx and tx */
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GELIC_NET_DESCR_PROTECTION_ERROR = 0x02, /* used in rx and tx */
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GELIC_NET_DESCR_FRAME_END = 0x04, /* used in rx */
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GELIC_NET_DESCR_FORCE_END = 0x05, /* used in rx and tx */
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GELIC_NET_DESCR_CARDOWNED = 0x0a, /* used in rx and tx */
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GELIC_NET_DESCR_NOT_IN_USE = 0x0b /* any other value */
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/* [1] */
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GELIC_DESCR_TX_DMA_CHAIN_END = 0x00000002, /* DMA terminated
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* due to chain end
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*/
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};
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#define GELIC_DESCR_DMA_CMD_NO_CHKSUM \
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(GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
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GELIC_DESCR_TX_DMA_NO_CHKSUM)
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#define GELIC_DESCR_DMA_CMD_TCP_CHKSUM \
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(GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
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GELIC_DESCR_TX_DMA_TCP_CHKSUM)
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#define GELIC_DESCR_DMA_CMD_UDP_CHKSUM \
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(GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
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GELIC_DESCR_TX_DMA_UDP_CHKSUM)
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enum gelic_descr_rx_dma_status {
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/* [ 1 ] */
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GELIC_DESCR_RX_DMA_CHAIN_END = 0x00000002, /* DMA terminated
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* due to chain end
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*/
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};
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/* for lv1_net_control */
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#define GELIC_NET_GET_MAC_ADDRESS 0x0000000000000001
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#define GELIC_NET_GET_ETH_PORT_STATUS 0x0000000000000002
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#define GELIC_NET_SET_NEGOTIATION_MODE 0x0000000000000003
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#define GELIC_NET_GET_VLAN_ID 0x0000000000000004
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enum gelic_lv1_net_control_code {
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GELIC_LV1_GET_MAC_ADDRESS = 1,
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GELIC_LV1_GET_ETH_PORT_STATUS = 2,
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GELIC_LV1_SET_NEGOTIATION_MODE = 3,
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GELIC_LV1_GET_VLAN_ID = 4,
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};
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#define GELIC_NET_LINK_UP 0x0000000000000001
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#define GELIC_NET_FULL_DUPLEX 0x0000000000000002
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#define GELIC_NET_AUTO_NEG 0x0000000000000004
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#define GELIC_NET_SPEED_10 0x0000000000000010
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#define GELIC_NET_SPEED_100 0x0000000000000020
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#define GELIC_NET_SPEED_1000 0x0000000000000040
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/* status returened from GET_ETH_PORT_STATUS */
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enum gelic_lv1_ether_port_status {
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GELIC_LV1_ETHER_LINK_UP = 0x0000000000000001L,
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GELIC_LV1_ETHER_FULL_DUPLEX = 0x0000000000000002L,
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GELIC_LV1_ETHER_AUTO_NEG = 0x0000000000000004L,
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#define GELIC_NET_VLAN_ALL 0x0000000000000001
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#define GELIC_NET_VLAN_WIRED 0x0000000000000002
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#define GELIC_NET_VLAN_WIRELESS 0x0000000000000003
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#define GELIC_NET_VLAN_PSP 0x0000000000000004
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#define GELIC_NET_VLAN_PORT0 0x0000000000000010
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#define GELIC_NET_VLAN_PORT1 0x0000000000000011
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#define GELIC_NET_VLAN_PORT2 0x0000000000000012
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#define GELIC_NET_VLAN_DAEMON_CLIENT_BSS 0x0000000000000013
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#define GELIC_NET_VLAN_LIBERO_CLIENT_BSS 0x0000000000000014
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#define GELIC_NET_VLAN_NO_ENTRY -6
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GELIC_LV1_ETHER_SPEED_10 = 0x0000000000000010L,
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GELIC_LV1_ETHER_SPEED_100 = 0x0000000000000020L,
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GELIC_LV1_ETHER_SPEED_1000 = 0x0000000000000040L,
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GELIC_LV1_ETHER_SPEED_MASK = 0x0000000000000070L
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};
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#define GELIC_NET_PORT 2 /* for port status */
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enum gelic_lv1_vlan_index {
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/* for outgoing packets */
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GELIC_LV1_VLAN_TX_ETHERNET = 0x0000000000000002L,
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GELIC_LV1_VLAN_TX_WIRELESS = 0x0000000000000003L,
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/* for incoming packets */
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GELIC_LV1_VLAN_RX_ETHERNET = 0x0000000000000012L,
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GELIC_LV1_VLAN_RX_WIRELESS = 0x0000000000000013L
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};
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/* size of hardware part of gelic descriptor */
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#define GELIC_NET_DESCR_SIZE (32)
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struct gelic_net_descr {
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#define GELIC_DESCR_SIZE (32)
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struct gelic_descr {
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/* as defined by the hardware */
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__be32 buf_addr;
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__be32 buf_size;
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@ -181,18 +220,18 @@ struct gelic_net_descr {
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/* used in the driver */
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struct sk_buff *skb;
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dma_addr_t bus_addr;
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struct gelic_net_descr *next;
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struct gelic_net_descr *prev;
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struct gelic_descr *next;
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struct gelic_descr *prev;
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struct vlan_ethhdr vlan;
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} __attribute__((aligned(32)));
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struct gelic_net_descr_chain {
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struct gelic_descr_chain {
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/* we walk from tail to head */
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struct gelic_net_descr *head;
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struct gelic_net_descr *tail;
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struct gelic_descr *head;
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struct gelic_descr *tail;
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};
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struct gelic_net_card {
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struct gelic_card {
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struct net_device *netdev;
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struct napi_struct napi;
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/*
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@ -207,8 +246,8 @@ struct gelic_net_card {
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u32 vlan_id[GELIC_NET_VLAN_MAX];
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int vlan_index;
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struct gelic_net_descr_chain tx_chain;
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struct gelic_net_descr_chain rx_chain;
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struct gelic_descr_chain tx_chain;
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struct gelic_descr_chain rx_chain;
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int rx_dma_restart_required;
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/* gurad dmac descriptor chain*/
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spinlock_t chain_lock;
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@ -222,8 +261,8 @@ struct gelic_net_card {
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atomic_t tx_timeout_task_counter;
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wait_queue_head_t waitq;
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struct gelic_net_descr *tx_top, *rx_top;
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struct gelic_net_descr descr[0];
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struct gelic_descr *tx_top, *rx_top;
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struct gelic_descr descr[0];
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};
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