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drm/intel: Fix initialization if startup happens in interlaced mode [v2]
My EFI BIOS starts the graphics card up in my projector's preferred EDID mode, 1080@60i. The Intel driver does not clear all the interlaced bits. This patch introduces a new PIPECONF_INTERLACE_MASK define and uses it to restore progressive mode. Signed-of-by: Christian Schmidt <schmidt@digadd.de> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -2312,6 +2312,7 @@
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#define PIPECONF_PROGRESSIVE (0 << 21)
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#define PIPECONF_PROGRESSIVE (0 << 21)
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#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
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#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
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#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
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#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
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#define PIPECONF_INTERLACE_MASK (7 << 21)
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#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
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#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
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#define PIPECONF_BPP_MASK (0x000000e0)
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#define PIPECONF_BPP_MASK (0x000000e0)
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#define PIPECONF_BPP_8 (0<<5)
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#define PIPECONF_BPP_8 (0<<5)
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@ -5136,7 +5136,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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adjusted_mode->crtc_vsync_end -= 1;
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adjusted_mode->crtc_vsync_end -= 1;
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adjusted_mode->crtc_vsync_start -= 1;
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adjusted_mode->crtc_vsync_start -= 1;
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} else
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} else
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pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
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pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */
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I915_WRITE(HTOTAL(pipe),
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I915_WRITE(HTOTAL(pipe),
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(adjusted_mode->crtc_hdisplay - 1) |
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(adjusted_mode->crtc_hdisplay - 1) |
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