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soc: qcom: geni-se: Add SPI Device mode support for GENI based QuPv3

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Add device mode supported registers and masks.

Signed-off-by: Praveen Talari <quic_ptalari@quicinc.com>
Reviewed-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>
Link: https://lore.kernel.org/r/20230714042203.14251-2-quic_ptalari@quicinc.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Praveen Talari 2023-07-14 09:52:02 +05:30 committed by Mark Brown
parent 893aa09ee5
commit 59bbe86bb2
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1 changed files with 9 additions and 0 deletions
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9
include/linux/soc/qcom/geni-se.h
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@ -35,6 +35,7 @@ enum geni_se_protocol_type {
GENI_SE_UART,
GENI_SE_I2C,
GENI_SE_I3C,
GENI_SE_SPI_SLAVE,
};
struct geni_wrapper;
@ -73,12 +74,14 @@ struct geni_se {
/* Common SE registers */
#define GENI_FORCE_DEFAULT_REG 0x20
#define GENI_OUTPUT_CTRL 0x24
#define SE_GENI_STATUS 0x40
#define GENI_SER_M_CLK_CFG 0x48
#define GENI_SER_S_CLK_CFG 0x4c
#define GENI_IF_DISABLE_RO 0x64
#define GENI_FW_REVISION_RO 0x68
#define SE_GENI_CLK_SEL 0x7c
#define SE_GENI_CFG_SEQ_START 0x84
#define SE_GENI_DMA_MODE_EN 0x258
#define SE_GENI_M_CMD0 0x600
#define SE_GENI_M_CMD_CTRL_REG 0x604
@ -111,6 +114,9 @@ struct geni_se {
/* GENI_FORCE_DEFAULT_REG fields */
#define FORCE_DEFAULT BIT(0)
/* GENI_OUTPUT_CTRL fields */
#define GENI_IO_MUX_0_EN BIT(0)
/* GENI_STATUS fields */
#define M_GENI_CMD_ACTIVE BIT(0)
#define S_GENI_CMD_ACTIVE BIT(12)
@ -130,6 +136,9 @@ struct geni_se {
/* GENI_CLK_SEL fields */
#define CLK_SEL_MSK GENMASK(2, 0)
/* SE_GENI_CFG_SEQ_START fields */
#define START_TRIGGER BIT(0)
/* SE_GENI_DMA_MODE_EN */
#define GENI_DMA_MODE_EN BIT(0)