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Renesas ARM Based SoC sh73a0 CCF Updates for v3.20
* Add sh73a0 CCF support -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIbBAABAgAGBQJUoJScAAoJENfPZGlqN0++sooP92KxIGVy7MKx/w5BSpDuePVc 4hkqvnsVhhAoZ/deNopVhEhYabHEkf/G3Feeh3Zahr1RRSCZf2Tz2FY6+FiP22wn 42CQjs8fmfHM4ibGqZpfqu/2M+nW+ceJ3c89F+l2M8IUTDuAt0SL/pUKo7fxczUC cfx3ZLRARpZH7eR/lyialrJInojldxb0GeK5sfacOCOXsOSr8Dn9LwD1o7P+TU3M MqL+e/VBXwBVElv5+2pk1p/x4Dhauoj6xEbSW6Nn0AjD9PP2HwxR3qLaltrbU7ad U8KKQON9P5cn4i/lblpiKvMAEE8lcpgGMnr0UE6+k2+z/oAQM31ooZhRuMoV1MsM JkPHx0iDhqWAxEM3a+bx7jEieH8EzG9fLzJfaU5ga4HhMdfl1pY1NYWaZe4ZiPqE K3Y3bFPkBTOrP1OOEXaNpIQdmKTrv0yAb4Y0PkxwPA9NGxWf+ci8ut/eqC2uyYFE qf8Jp+OB3QDNMObvhi6y44uPHTVEBDFOCwit0muJ70IrzOqpVVwyaMYsFtvrGnuu WvNBanNfpj1/1HkSkAtuAJasJ+LtIGH8cxvuIrfj3g+O55kJVzsCJFoEb1rzdmZp hjylXR07GRiCaXU24xxqYSSBWP6WMW9i2sIxYros241sDnsWyu3ydXlZBL0mh3rs 79ax88sekME0duLB720= =zFTr -----END PGP SIGNATURE----- Merge tag 'renesas-sh73a0-ccf-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers Merge "Renesas ARM Based SoC sh73a0 CCF Updates for v3.20" from Simon Horman: * Add sh73a0 CCF support * tag 'renesas-sh73a0-ccf-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: sh73a0: disable legacy clock initialization ARM: shmobile: sh73a0: add MSTP clock assignments to DT ARM: shmobile: kzm9g-reference: Common clock framework DT description ARM: shmobile: sh73a0: Common clock framework DT description ARM: shmobile: sh73a0: Add CPG register bits header clk: shmobile: sh73a0 common clock framework implementation Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
58bdda1b57
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@ -0,0 +1,35 @@
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These bindings should be considered EXPERIMENTAL for now.
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* Renesas SH73A0 Clock Pulse Generator (CPG)
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The CPG generates core clocks for the SH73A0 SoC. It includes four PLLs
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and several fixed ratio dividers.
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Required Properties:
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- compatible: Must be "renesas,sh73a0-cpg-clocks"
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- reg: Base address and length of the memory resource used by the CPG
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- clocks: Reference to the parent clocks ("extal1" and "extal2")
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are "main",
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"pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
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"m1", "m2", "z", "zx", and "hp".
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Example
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-------
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,sh73a0-cpg-clocks";
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reg = <0 0xe6150000 0 0x10000>;
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clocks = <&extal1_clk>, <&extal2_clk>;
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#clock-cells = <1>;
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clock-output-names = "main", "pll0", "pll1", "pll2",
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"pll3", "dsi0phy", "dsi1phy",
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"zg", "m3", "b", "m1", "m2",
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"z", "zx", "hp";
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};
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@ -182,6 +182,10 @@
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status = "ok";
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};
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&extal2_clk {
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clock-frequency = <48000000>;
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};
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&i2c0 {
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status = "okay";
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as3711@40 {
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@ -10,6 +10,7 @@
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/include/ "skeleton.dtsi"
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#include <dt-bindings/clock/sh73a0-clock.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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@ -55,6 +56,8 @@
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renesas,channels-mask = <0x3f>;
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clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
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clock-names = "fck";
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status = "disabled";
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};
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@ -144,6 +147,7 @@
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0 168 IRQ_TYPE_LEVEL_HIGH
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0 169 IRQ_TYPE_LEVEL_HIGH
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0 170 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
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status = "disabled";
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};
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@ -156,6 +160,7 @@
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0 52 IRQ_TYPE_LEVEL_HIGH
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0 53 IRQ_TYPE_LEVEL_HIGH
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0 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
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status = "disabled";
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};
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@ -168,6 +173,7 @@
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0 172 IRQ_TYPE_LEVEL_HIGH
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0 173 IRQ_TYPE_LEVEL_HIGH
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0 174 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
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status = "disabled";
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};
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@ -180,6 +186,7 @@
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0 184 IRQ_TYPE_LEVEL_HIGH
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0 185 IRQ_TYPE_LEVEL_HIGH
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0 186 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
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status = "disabled";
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};
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@ -192,6 +199,7 @@
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0 188 IRQ_TYPE_LEVEL_HIGH
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0 189 IRQ_TYPE_LEVEL_HIGH
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0 190 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
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status = "disabled";
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};
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@ -200,6 +208,7 @@
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reg = <0xe6bd0000 0x100>;
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interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
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0 141 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
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reg-io-width = <4>;
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status = "disabled";
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};
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@ -210,6 +219,7 @@
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interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH
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0 84 IRQ_TYPE_LEVEL_HIGH
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0 85 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
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cap-sd-highspeed;
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status = "disabled";
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};
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@ -220,6 +230,7 @@
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reg = <0xee120000 0x100>;
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interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
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0 89 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
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toshiba,mmc-wrprotect-disable;
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cap-sd-highspeed;
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status = "disabled";
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@ -230,6 +241,7 @@
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reg = <0xee140000 0x100>;
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interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
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0 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
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toshiba,mmc-wrprotect-disable;
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cap-sd-highspeed;
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status = "disabled";
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@ -239,6 +251,8 @@
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6c40000 0x100>;
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interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -246,6 +260,8 @@
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6c50000 0x100>;
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interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -253,6 +269,8 @@
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6c60000 0x100>;
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interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -260,6 +278,8 @@
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6c70000 0x100>;
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interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -267,6 +287,8 @@
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6c80000 0x100>;
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interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -274,6 +296,8 @@
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6cb0000 0x100>;
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interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -281,6 +305,8 @@
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6cc0000 0x100>;
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interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -288,6 +314,8 @@
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6cd0000 0x100>;
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interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -295,6 +323,8 @@
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compatible = "renesas,scifb-sh73a0", "renesas,scifb";
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reg = <0xe6c30000 0x100>;
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interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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@ -322,4 +352,332 @@
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interrupts = <0 146 0x4>;
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status = "disabled";
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* External root clocks */
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extalr_clk: extalr_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "extalr";
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};
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extal1_clk: extal1_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "extal1";
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};
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extal2_clk: extal2_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "extal2";
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};
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extcki_clk: extcki_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "extcki";
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};
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fsiack_clk: fsiack_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "fsiack";
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};
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fsibck_clk: fsibck_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "fsibck";
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};
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/* Special CPG clocks */
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,sh73a0-cpg-clocks";
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reg = <0xe6150000 0x10000>;
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clocks = <&extal1_clk>, <&extal2_clk>;
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#clock-cells = <1>;
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clock-output-names = "main", "pll0", "pll1", "pll2",
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"pll3", "dsi0phy", "dsi1phy",
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"zg", "m3", "b", "m1", "m2",
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"z", "zx", "hp";
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};
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/* Variable factor clocks (DIV6) */
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vclk1_clk: vclk1_clk@e6150008 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150008 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "vclk1";
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};
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vclk2_clk: vclk2_clk@e615000c {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe615000c 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "vclk2";
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};
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vclk3_clk: vclk3_clk@e615001c {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe615001c 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "vclk3";
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};
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zb_clk: zb_clk@e6150010 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150010 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "zb";
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};
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flctl_clk: flctl_clk@e6150014 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150014 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "flctlck";
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};
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sdhi0_clk: sdhi0_clk@e6150074 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150074 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sdhi0ck";
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};
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sdhi1_clk: sdhi1_clk@e6150078 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150078 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sdhi1ck";
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};
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sdhi2_clk: sdhi2_clk@e615007c {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe615007c 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sdhi2ck";
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};
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fsia_clk: fsia_clk@e6150018 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150018 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "fsia";
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};
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fsib_clk: fsib_clk@e6150090 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150090 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "fsib";
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};
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sub_clk: sub_clk@e6150080 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150080 4>;
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clocks = <&extal2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sub";
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};
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spua_clk: spua_clk@e6150084 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150084 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "spua";
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};
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spuv_clk: spuv_clk@e6150094 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150094 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "spuv";
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};
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msu_clk: msu_clk@e6150088 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150088 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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||||
clock-output-names = "msu";
|
||||
};
|
||||
hsi_clk: hsi_clk@e615008c {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe615008c 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "hsi";
|
||||
};
|
||||
mfg1_clk: mfg1_clk@e6150098 {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150098 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mfg1";
|
||||
};
|
||||
mfg2_clk: mfg2_clk@e615009c {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe615009c 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mfg2";
|
||||
};
|
||||
dsit_clk: dsit_clk@e6150060 {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150060 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "dsit";
|
||||
};
|
||||
dsi0p_clk: dsi0p_clk@e6150064 {
|
||||
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe6150064 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "dsi0pck";
|
||||
};
|
||||
|
||||
/* Fixed factor clocks */
|
||||
main_div2_clk: main_div2_clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "main_div2";
|
||||
};
|
||||
pll1_div2_clk: pll1_div2_clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "pll1_div2";
|
||||
};
|
||||
pll1_div7_clk: pll1_div7_clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <7>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "pll1_div7";
|
||||
};
|
||||
pll1_div13_clk: pll1_div13_clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <13>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "pll1_div13";
|
||||
};
|
||||
twd_clk: twd_clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks SH73A0_CLK_Z>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "twd";
|
||||
};
|
||||
|
||||
/* Gate clocks */
|
||||
mstp0_clks: mstp0_clks@e6150130 {
|
||||
compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0xe6150130 4>, <0xe6150030 4>;
|
||||
clocks = <&cpg_clocks SH73A0_CLK_HP>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
SH73A0_CLK_IIC2
|
||||
>;
|
||||
clock-output-names =
|
||||
"iic2";
|
||||
};
|
||||
mstp1_clks: mstp1_clks@e6150134 {
|
||||
compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0xe6150134 4>, <0xe6150038 4>;
|
||||
clocks = <&cpg_clocks SH73A0_CLK_B>,
|
||||
<&cpg_clocks SH73A0_CLK_B>,
|
||||
<&cpg_clocks SH73A0_CLK_B>,
|
||||
<&cpg_clocks SH73A0_CLK_B>,
|
||||
<&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
|
||||
<&cpg_clocks SH73A0_CLK_HP>,
|
||||
<&cpg_clocks SH73A0_CLK_ZG>,
|
||||
<&cpg_clocks SH73A0_CLK_B>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
|
||||
SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
|
||||
SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
|
||||
SH73A0_CLK_IIC0 SH73A0_CLK_SGX
|
||||
SH73A0_CLK_LCDC0
|
||||
>;
|
||||
clock-output-names =
|
||||
"ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
|
||||
"tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
|
||||
};
|
||||
mstp2_clks: mstp2_clks@e6150138 {
|
||||
compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0xe6150138 4>, <0xe6150040 4>;
|
||||
clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
|
||||
<&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
|
||||
<&sub_clk>, <&sub_clk>, <&sub_clk>, <&sub_clk>,
|
||||
<&sub_clk>, <&sub_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
|
||||
SH73A0_CLK_MP_DMAC SH73A0_CLK_SCIFA5
|
||||
SH73A0_CLK_SCIFB SH73A0_CLK_SCIFA0
|
||||
SH73A0_CLK_SCIFA1 SH73A0_CLK_SCIFA2
|
||||
SH73A0_CLK_SCIFA3 SH73A0_CLK_SCIFA4
|
||||
>;
|
||||
clock-output-names =
|
||||
"scifa7", "sy_dmac", "mp_dmac", "scifa5",
|
||||
"scifb", "scifa0", "scifa1", "scifa2",
|
||||
"scifa3", "scifa4";
|
||||
};
|
||||
mstp3_clks: mstp3_clks@e615013c {
|
||||
compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0xe615013c 4>, <0xe6150048 4>;
|
||||
clocks = <&sub_clk>, <&extalr_clk>,
|
||||
<&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
|
||||
<&cpg_clocks SH73A0_CLK_HP>,
|
||||
<&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
|
||||
<&sdhi0_clk>, <&sdhi1_clk>,
|
||||
<&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
|
||||
<&main_div2_clk>, <&main_div2_clk>,
|
||||
<&main_div2_clk>, <&main_div2_clk>,
|
||||
<&main_div2_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
|
||||
SH73A0_CLK_FSI SH73A0_CLK_IRDA
|
||||
SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
|
||||
SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
|
||||
SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
|
||||
SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
|
||||
SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
|
||||
SH73A0_CLK_TPU4
|
||||
>;
|
||||
clock-output-names =
|
||||
"scifa6", "cmt1", "fsi", "irda", "iic1",
|
||||
"usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
|
||||
"tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
|
||||
};
|
||||
mstp4_clks: mstp4_clks@e6150140 {
|
||||
compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0xe6150140 4>, <0xe615004c 4>;
|
||||
clocks = <&cpg_clocks SH73A0_CLK_HP>,
|
||||
<&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
|
||||
SH73A0_CLK_KEYSC
|
||||
>;
|
||||
clock-output-names =
|
||||
"iic3", "iic4", "keysc";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -763,7 +763,9 @@ void __init __weak sh73a0_register_twd(void) { }
|
|||
void __init sh73a0_earlytimer_init(void)
|
||||
{
|
||||
shmobile_init_delay();
|
||||
#ifndef CONFIG_COMMON_CLK
|
||||
sh73a0_clock_init();
|
||||
#endif
|
||||
shmobile_earlytimer_init();
|
||||
sh73a0_register_twd();
|
||||
}
|
||||
|
|
@ -782,8 +784,9 @@ void __init sh73a0_add_early_devices(void)
|
|||
void __init sh73a0_add_standard_devices_dt(void)
|
||||
{
|
||||
/* clocks are setup late during boot in the case of DT */
|
||||
#ifndef CONFIG_COMMON_CLK
|
||||
sh73a0_clock_init();
|
||||
|
||||
#endif
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -5,5 +5,6 @@ obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
|
|||
obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o
|
||||
obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o
|
||||
obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o
|
||||
obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o
|
||||
obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-div6.o
|
||||
obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-mstp.o
|
||||
|
|
|
|||
218
drivers/clk/shmobile/clk-sh73a0.c
Normal file
218
drivers/clk/shmobile/clk-sh73a0.c
Normal file
|
|
@ -0,0 +1,218 @@
|
|||
/*
|
||||
* sh73a0 Core CPG Clocks
|
||||
*
|
||||
* Copyright (C) 2014 Ulrich Hecht
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk/shmobile.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
struct sh73a0_cpg {
|
||||
struct clk_onecell_data data;
|
||||
spinlock_t lock;
|
||||
void __iomem *reg;
|
||||
};
|
||||
|
||||
#define CPG_FRQCRA 0x00
|
||||
#define CPG_FRQCRB 0x04
|
||||
#define CPG_SD0CKCR 0x74
|
||||
#define CPG_SD1CKCR 0x78
|
||||
#define CPG_SD2CKCR 0x7c
|
||||
#define CPG_PLLECR 0xd0
|
||||
#define CPG_PLL0CR 0xd8
|
||||
#define CPG_PLL1CR 0x28
|
||||
#define CPG_PLL2CR 0x2c
|
||||
#define CPG_PLL3CR 0xdc
|
||||
#define CPG_CKSCR 0xc0
|
||||
#define CPG_DSI0PHYCR 0x6c
|
||||
#define CPG_DSI1PHYCR 0x70
|
||||
|
||||
#define CLK_ENABLE_ON_INIT BIT(0)
|
||||
|
||||
struct div4_clk {
|
||||
const char *name;
|
||||
const char *parent;
|
||||
unsigned int reg;
|
||||
unsigned int shift;
|
||||
};
|
||||
|
||||
static struct div4_clk div4_clks[] = {
|
||||
{ "zg", "pll0", CPG_FRQCRA, 16 },
|
||||
{ "m3", "pll1", CPG_FRQCRA, 12 },
|
||||
{ "b", "pll1", CPG_FRQCRA, 8 },
|
||||
{ "m1", "pll1", CPG_FRQCRA, 4 },
|
||||
{ "m2", "pll1", CPG_FRQCRA, 0 },
|
||||
{ "zx", "pll1", CPG_FRQCRB, 12 },
|
||||
{ "hp", "pll1", CPG_FRQCRB, 4 },
|
||||
{ NULL, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_div_table div4_div_table[] = {
|
||||
{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
|
||||
{ 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
|
||||
{ 12, 7 }, { 0, 0 }
|
||||
};
|
||||
|
||||
static const struct clk_div_table z_div_table[] = {
|
||||
/* ZSEL == 0 */
|
||||
{ 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1 }, { 4, 1 }, { 5, 1 },
|
||||
{ 6, 1 }, { 7, 1 }, { 8, 1 }, { 9, 1 }, { 10, 1 }, { 11, 1 },
|
||||
{ 12, 1 }, { 13, 1 }, { 14, 1 }, { 15, 1 },
|
||||
/* ZSEL == 1 */
|
||||
{ 16, 2 }, { 17, 3 }, { 18, 4 }, { 19, 6 }, { 20, 8 }, { 21, 12 },
|
||||
{ 22, 16 }, { 24, 24 }, { 27, 48 }, { 0, 0 }
|
||||
};
|
||||
|
||||
static struct clk * __init
|
||||
sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
|
||||
const char *name)
|
||||
{
|
||||
const struct clk_div_table *table = NULL;
|
||||
unsigned int shift, reg, width;
|
||||
const char *parent_name;
|
||||
unsigned int mult = 1;
|
||||
unsigned int div = 1;
|
||||
|
||||
if (!strcmp(name, "main")) {
|
||||
/* extal1, extal1_div2, extal2, extal2_div2 */
|
||||
u32 parent_idx = (clk_readl(cpg->reg + CPG_CKSCR) >> 28) & 3;
|
||||
|
||||
parent_name = of_clk_get_parent_name(np, parent_idx >> 1);
|
||||
div = (parent_idx & 1) + 1;
|
||||
} else if (!strncmp(name, "pll", 3)) {
|
||||
void __iomem *enable_reg = cpg->reg;
|
||||
u32 enable_bit = name[3] - '0';
|
||||
|
||||
parent_name = "main";
|
||||
switch (enable_bit) {
|
||||
case 0:
|
||||
enable_reg += CPG_PLL0CR;
|
||||
break;
|
||||
case 1:
|
||||
enable_reg += CPG_PLL1CR;
|
||||
break;
|
||||
case 2:
|
||||
enable_reg += CPG_PLL2CR;
|
||||
break;
|
||||
case 3:
|
||||
enable_reg += CPG_PLL3CR;
|
||||
break;
|
||||
default:
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
if (clk_readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) {
|
||||
mult = ((clk_readl(enable_reg) >> 24) & 0x3f) + 1;
|
||||
/* handle CFG bit for PLL1 and PLL2 */
|
||||
if (enable_bit == 1 || enable_bit == 2)
|
||||
if (clk_readl(enable_reg) & BIT(20))
|
||||
mult *= 2;
|
||||
}
|
||||
} else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) {
|
||||
u32 phy_no = name[3] - '0';
|
||||
void __iomem *dsi_reg = cpg->reg +
|
||||
(phy_no ? CPG_DSI1PHYCR : CPG_DSI0PHYCR);
|
||||
|
||||
parent_name = phy_no ? "dsi1pck" : "dsi0pck";
|
||||
mult = __raw_readl(dsi_reg);
|
||||
if (!(mult & 0x8000))
|
||||
mult = 1;
|
||||
else
|
||||
mult = (mult & 0x3f) + 1;
|
||||
} else if (!strcmp(name, "z")) {
|
||||
parent_name = "pll0";
|
||||
table = z_div_table;
|
||||
reg = CPG_FRQCRB;
|
||||
shift = 24;
|
||||
width = 5;
|
||||
} else {
|
||||
struct div4_clk *c;
|
||||
|
||||
for (c = div4_clks; c->name; c++) {
|
||||
if (!strcmp(name, c->name)) {
|
||||
parent_name = c->parent;
|
||||
table = div4_div_table;
|
||||
reg = c->reg;
|
||||
shift = c->shift;
|
||||
width = 4;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!c->name)
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
if (!table) {
|
||||
return clk_register_fixed_factor(NULL, name, parent_name, 0,
|
||||
mult, div);
|
||||
} else {
|
||||
return clk_register_divider_table(NULL, name, parent_name, 0,
|
||||
cpg->reg + reg, shift, width, 0,
|
||||
table, &cpg->lock);
|
||||
}
|
||||
}
|
||||
|
||||
static void __init sh73a0_cpg_clocks_init(struct device_node *np)
|
||||
{
|
||||
struct sh73a0_cpg *cpg;
|
||||
struct clk **clks;
|
||||
unsigned int i;
|
||||
int num_clks;
|
||||
|
||||
num_clks = of_property_count_strings(np, "clock-output-names");
|
||||
if (num_clks < 0) {
|
||||
pr_err("%s: failed to count clocks\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
|
||||
clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
|
||||
if (cpg == NULL || clks == NULL) {
|
||||
/* We're leaking memory on purpose, there's no point in cleaning
|
||||
* up as the system won't boot anyway.
|
||||
*/
|
||||
return;
|
||||
}
|
||||
|
||||
spin_lock_init(&cpg->lock);
|
||||
|
||||
cpg->data.clks = clks;
|
||||
cpg->data.clk_num = num_clks;
|
||||
|
||||
cpg->reg = of_iomap(np, 0);
|
||||
if (WARN_ON(cpg->reg == NULL))
|
||||
return;
|
||||
|
||||
/* Set SDHI clocks to a known state */
|
||||
clk_writel(0x108, cpg->reg + CPG_SD0CKCR);
|
||||
clk_writel(0x108, cpg->reg + CPG_SD1CKCR);
|
||||
clk_writel(0x108, cpg->reg + CPG_SD2CKCR);
|
||||
|
||||
for (i = 0; i < num_clks; ++i) {
|
||||
const char *name;
|
||||
struct clk *clk;
|
||||
|
||||
of_property_read_string_index(np, "clock-output-names", i,
|
||||
&name);
|
||||
|
||||
clk = sh73a0_cpg_register_clock(np, cpg, name);
|
||||
if (IS_ERR(clk))
|
||||
pr_err("%s: failed to register %s %s clock (%ld)\n",
|
||||
__func__, np->name, name, PTR_ERR(clk));
|
||||
else
|
||||
cpg->data.clks[i] = clk;
|
||||
}
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
|
||||
}
|
||||
CLK_OF_DECLARE(sh73a0_cpg_clks, "renesas,sh73a0-cpg-clocks",
|
||||
sh73a0_cpg_clocks_init);
|
||||
79
include/dt-bindings/clock/sh73a0-clock.h
Normal file
79
include/dt-bindings/clock/sh73a0-clock.h
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* Copyright 2014 Ulrich Hecht
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_SH73A0_H__
|
||||
#define __DT_BINDINGS_CLOCK_SH73A0_H__
|
||||
|
||||
/* CPG */
|
||||
#define SH73A0_CLK_MAIN 0
|
||||
#define SH73A0_CLK_PLL0 1
|
||||
#define SH73A0_CLK_PLL1 2
|
||||
#define SH73A0_CLK_PLL2 3
|
||||
#define SH73A0_CLK_PLL3 4
|
||||
#define SH73A0_CLK_DSI0PHY 5
|
||||
#define SH73A0_CLK_DSI1PHY 6
|
||||
#define SH73A0_CLK_ZG 7
|
||||
#define SH73A0_CLK_M3 8
|
||||
#define SH73A0_CLK_B 9
|
||||
#define SH73A0_CLK_M1 10
|
||||
#define SH73A0_CLK_M2 11
|
||||
#define SH73A0_CLK_Z 12
|
||||
#define SH73A0_CLK_ZX 13
|
||||
#define SH73A0_CLK_HP 14
|
||||
|
||||
/* MSTP0 */
|
||||
#define SH73A0_CLK_IIC2 1
|
||||
|
||||
/* MSTP1 */
|
||||
#define SH73A0_CLK_CEU1 29
|
||||
#define SH73A0_CLK_CSI2_RX1 28
|
||||
#define SH73A0_CLK_CEU0 27
|
||||
#define SH73A0_CLK_CSI2_RX0 26
|
||||
#define SH73A0_CLK_TMU0 25
|
||||
#define SH73A0_CLK_DSITX0 18
|
||||
#define SH73A0_CLK_IIC0 16
|
||||
#define SH73A0_CLK_SGX 12
|
||||
#define SH73A0_CLK_LCDC0 0
|
||||
|
||||
/* MSTP2 */
|
||||
#define SH73A0_CLK_SCIFA7 19
|
||||
#define SH73A0_CLK_SY_DMAC 18
|
||||
#define SH73A0_CLK_MP_DMAC 17
|
||||
#define SH73A0_CLK_SCIFA5 7
|
||||
#define SH73A0_CLK_SCIFB 6
|
||||
#define SH73A0_CLK_SCIFA0 4
|
||||
#define SH73A0_CLK_SCIFA1 3
|
||||
#define SH73A0_CLK_SCIFA2 2
|
||||
#define SH73A0_CLK_SCIFA3 1
|
||||
#define SH73A0_CLK_SCIFA4 0
|
||||
|
||||
/* MSTP3 */
|
||||
#define SH73A0_CLK_SCIFA6 31
|
||||
#define SH73A0_CLK_CMT1 29
|
||||
#define SH73A0_CLK_FSI 28
|
||||
#define SH73A0_CLK_IRDA 25
|
||||
#define SH73A0_CLK_IIC1 23
|
||||
#define SH73A0_CLK_USB 22
|
||||
#define SH73A0_CLK_FLCTL 15
|
||||
#define SH73A0_CLK_SDHI0 14
|
||||
#define SH73A0_CLK_SDHI1 13
|
||||
#define SH73A0_CLK_MMCIF0 12
|
||||
#define SH73A0_CLK_SDHI2 11
|
||||
#define SH73A0_CLK_TPU0 4
|
||||
#define SH73A0_CLK_TPU1 3
|
||||
#define SH73A0_CLK_TPU2 2
|
||||
#define SH73A0_CLK_TPU3 1
|
||||
#define SH73A0_CLK_TPU4 0
|
||||
|
||||
/* MSTP4 */
|
||||
#define SH73A0_CLK_IIC3 11
|
||||
#define SH73A0_CLK_IIC4 10
|
||||
#define SH73A0_CLK_KEYSC 3
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user